Skip to content

Latest commit

 

History

History
13 lines (9 loc) · 437 Bytes

File metadata and controls

13 lines (9 loc) · 437 Bytes

FPGA_AI_Verilog

This project is a modified version of FPGA_AI by @nhma20.

Changes from original:

  • Added SystemVerilog implementation for simulation
  • Quantization workflow for fixed-point neural networks
  • Python/Verilator hybrid GUI, etc.

Original code and documentation copyright (c) 2022 nhma20. Modifications (c) 2024 [your name].

See LICENSE for details.