Lint: Fix lint issues in markdown tables

Author: isak-jakobsson

object-detection-cv25/README.md

@@ -294,13 +294,13 @@ Depending on selected chip, different output is received. The label file is used
 
 In the system log the chip is sometimes only mentioned as a string, they are mapped as follows:
 
-| Chips | Larod 1 (int) | Larod 3 |
-|-------|--------------|------------------|
-| CPU with TensorFlow Lite | 2 | cpu-tflite |
-| Google TPU | 4 | google-edge-tpu-tflite |
-| Ambarella CVFlow (NN) | 6 | ambarella-cvflow |
-| ARTPEC-8 DLPU | 12 | axis-a8-dlpu-tflite |
-| ARTPEC-9 DLPU | - | a9-dlpu-tflite |
+| Chips                    | Larod 1 (int) | Larod 3                |
+| ------------------------ | ------------- | ---------------------- |
+| CPU with TensorFlow Lite | 2             | cpu-tflite             |
+| Google TPU               | 4             | google-edge-tpu-tflite |
+| Ambarella CVFlow (NN)    | 6             | ambarella-cvflow       |
+| ARTPEC-8 DLPU            | 12            | axis-a8-dlpu-tflite    |
+| ARTPEC-9 DLPU            | -             | a9-dlpu-tflite         |
 
 There are four outputs from MobileNet SSD v2 (COCO) model. The number of detections, cLasses, scores, and locations are shown as below. The four location numbers stand for \[top, left, bottom, right\]. By the way, currently the saved images will be overwritten continuously, so those saved images might not all from the detections of the last frame, if the number of detections is less than previous detection numbers.
 

tensorflow-to-larod/README.md

@@ -122,11 +122,11 @@ be done using less precision. This generally results in significantly lower
 inference latency and model size with only a slight penalty to the model's
 accuracy.
 
-| Chip      | Supported precision  |
-|---------- |------------------     |
-| Edge TPU  | INT8                  |
-| Common CPUs       | FP32, INT8            |
-| Common GPUs       | FP32, FP16, INT8      |
+| Chip        | Supported precision |
+| ----------- | ------------------- |
+| Edge TPU    | INT8                |
+| Common CPUs | FP32, INT8          |
+| Common GPUs | FP32, FP16, INT8    |
 
 As noted in the first chapter, this example uses a camera equipped with an Edge TPU.
 As the Edge TPU chip **only** uses INT8 precision, the model will need to be quantized from

vdo-larod/README.md

@@ -276,13 +276,13 @@ Depending on the selected chip, different output is received.
 
 In previous larod versions, the chip was referred to as a number instead of a string. See the table below to understand the mapping:
 
-| Chips | Larod 1 (int) | Larod 3 |
-|-------|--------------|------------------|
-| CPU with TensorFlow Lite | 2 | cpu-tflite |
-| Google TPU | 4 | google-edge-tpu-tflite |
-| Ambarella CVFlow (NN) | 6 | ambarella-cvflow |
-| ARTPEC-8 DLPU | 12 | axis-a8-dlpu-tflite |
-| ARTPEC-9 DLPU | - | a9-dlpu-tflite |
+| Chips                    | Larod 1 (int) | Larod 3                |
+| ------------------------ | ------------- | ---------------------- |
+| CPU with TensorFlow Lite | 2             | cpu-tflite             |
+| Google TPU               | 4             | google-edge-tpu-tflite |
+| Ambarella CVFlow (NN)    | 6             | ambarella-cvflow       |
+| ARTPEC-8 DLPU            | 12            | axis-a8-dlpu-tflite    |
+| ARTPEC-9 DLPU            | -             | a9-dlpu-tflite         |
 
 #### Output - ARTPEC-8 with TensorFlow Lite