nrf5x: Add support for both NRF52 and NRF53

Changes in CMakeLists, NRF_HW_model_top.c, nrfx_common.c
and nrf_bsim_redef.h in order for the model to support
both the NRF52 and the NRF53 series.

Signed-off-by: Sletnes Bjørlo, Aurora <[email protected]>

Author: auroraslb

CMakeLists.txt

@@ -3,7 +3,7 @@
 
 # CMake file to compile this BabbleSim component as a west module in Zephyr
 
-if(CONFIG_BOARD_NRF52_BSIM)
+if(CONFIG_BOARD_NRF52_BSIM OR CONFIG_BOARD_NRF53_BSIM)
 
   if (NOT DEFINED ENV{BSIM_COMPONENTS_PATH})
     message(FATAL_ERROR "This Zephyr module requires the BabbleSim simulator.\
@@ -34,6 +34,15 @@ if(CONFIG_BOARD_NRF52_BSIM)
   zephyr_library_compile_definitions(NO_POSIX_CHEATS)
 
   file(GLOB_RECURSE HW_MODEL_SRCS . src/*.c)
+  if (CONFIG_BOARD_NRF52_BSIM)
+    list(REMOVE_ITEM HW_MODEL_SRCS ${CMAKE_CURRENT_SOURCE_DIR}/src/HW_models/NRF_DPPI.c)
+    list(REMOVE_ITEM HW_MODEL_SRCS ${CMAKE_CURRENT_SOURCE_DIR}/src/nrfx/hal/nrf_dppi.c)
+  elseif(CONFIG_BOARD_NRF53_BSIM)
+    list(REMOVE_ITEM HW_MODEL_SRCS ${CMAKE_CURRENT_SOURCE_DIR}/src/HW_models/NRF_PPI.c)
+    list(REMOVE_ITEM HW_MODEL_SRCS ${CMAKE_CURRENT_SOURCE_DIR}/src/nrfx/hal/nrf_ppi.c)
+  else()
+    message(FATAL_ERROR "Unknown board")
+  endif()
   zephyr_library_sources(${HW_MODEL_SRCS})
 
   zephyr_library_include_directories(

src/HW_models/NRF_HW_model_top.c

@@ -18,11 +18,16 @@
 #include "NRF_CLOCK.h"
 #include "NRF_RADIO.h"
 #include "NRF_FICR.h"
+#if defined(PPI_PRESENT)
 #include "NRF_PPI.h"
+#endif
 #include "NRF_TIMER.h"
 #include "irq_ctrl.h"
 #include "BLECrypt_if.h"
 #include "fake_timer.h"
+#if defined(DPPI_PRESENT)
+#include "NRF_DPPI.h"
+#endif
 
 void nrf_hw_models_free_all(){
   nrf_clock_clean_up();
@@ -33,7 +38,11 @@ void nrf_hw_models_free_all(){
   nrf_aar_clean_up();
   nrf_radio_clean_up();
   nrf_ficr_clean_up();
+#if defined(DPPI_PRESENT)
+  nrf_dppi_clean_up();
+#elif defined(PPI_PRESENT)
   nrf_ppi_clean_up();
+#endif
   nrf_timer_clean_up();
 }
 
@@ -60,7 +69,12 @@ void nrf_hw_initialize(nrf_hw_sub_args_t *args){
   nrf_aar_init();
   nrf_radio_init();
   nrf_ficr_init();
+#if defined(DPPI_PRESENT)
+  nrf_dppi_init();
+#elif defined(PPI_PRESENT)
   nrf_ppi_init();
+#endif
+
   nrf_timer_init();
   nrf_hw_find_next_timer_to_trigger();
 }

src/nrfx/drivers/nrfx_common.c

@@ -20,9 +20,16 @@ IRQn_Type nrfx_get_irq_number(void const * p_reg){
     ((intptr_t)p < (intptr_t)NRF_##per##nbr##_BASE + sizeof(NRF_##per##_Type))
 
   if (IS_PERIPHERAL_REG(p_reg, POWER,)) {
+#if !defined(NRF53_SERIES)
     return POWER_CLOCK_IRQn;
   } else if (IS_PERIPHERAL_REG(p_reg, CLOCK,)) {
     return POWER_CLOCK_IRQn;
+#endif
+#if defined(NRF53_SERIES)
+    return CLOCK_POWER_IRQn;
+  } else if (IS_PERIPHERAL_REG(p_reg, CLOCK,)) {
+    return CLOCK_POWER_IRQn;
+#endif
   } else if (IS_PERIPHERAL_REG(p_reg, RADIO,)) {
     return RADIO_IRQn;
   /*2-7*/
@@ -40,20 +47,35 @@ IRQn_Type nrfx_get_irq_number(void const * p_reg){
   } else if (IS_PERIPHERAL_REG(p_reg, ECB,)) {
       return ECB_IRQn;
   } else if (IS_PERIPHERAL_REG(p_reg, AAR,)) {
+#if !defined(NRF53_SERIES)
       return CCM_AAR_IRQn;
   } else if (IS_PERIPHERAL_REG(p_reg, CCM,)) {
       return CCM_AAR_IRQn;
+#endif
+#if defined(NRF53_SERIES)
+      return AAR_CCM_IRQn;
+  } else if (IS_PERIPHERAL_REG(p_reg, CCM,)) {
+      return AAR_CCM_IRQn;
+#endif
   /*16*/
   } else if (IS_PERIPHERAL_REG(p_reg, RTC, 1)) {
       return RTC1_IRQn;
   /*18-25*/
+#if !defined(NRF53_SERIES)
   } else if (IS_PERIPHERAL_REG(p_reg, TIMER,3)) {
       return TIMER3_IRQn;
   } else if (IS_PERIPHERAL_REG(p_reg, TIMER,4)) {
       return TIMER4_IRQn;
+#endif
   /*28-30*/
+#if defined(PPI_PRESENT)
   } else if (IS_PERIPHERAL_REG(p_reg, PPI,)) {
       return 0x1F;
+#endif
+#if defined(DPPI_PRESENT)
+  } else if (IS_PERIPHERAL_REG(p_reg, DPPIC,)) {
+      return 0x1F;
+#endif
   /*32-..*/
   } else {
     bs_trace_error_time_line("Tried to get the peripheral number of an address unknown to this HW models\n");

src/nrfx/mdk_replacements/nrf_bsim_redef.h

@@ -19,6 +19,7 @@ extern "C" {
 /*
  * Redefine the base addresses.
  */
+
 extern NRF_AAR_Type NRF_AAR_regs;
 #undef NRF_AAR_BASE
 #define NRF_AAR_BASE                      (&NRF_AAR_regs)
@@ -48,9 +49,13 @@ extern NRF_CLOCK_Type NRF_CLOCK_regs;
 extern NRF_FICR_Type NRF_FICR_regs;
 #undef NRF_FICR_BASE
 #define NRF_FICR_BASE                     (&NRF_FICR_regs)
+
+#if defined(NRF52_SERIES)
 extern NRF_PPI_Type NRF_PPI_regs;
 #undef NRF_PPI_BASE
 #define NRF_PPI_BASE                      (&NRF_PPI_regs)
+#endif
+
 extern NRF_TIMER_Type NRF_TIMER_regs[];
 #undef NRF_TIMER0_BASE
 #define NRF_TIMER0_BASE                   (&NRF_TIMER_regs[0])
@@ -75,6 +80,84 @@ extern NRF_NVMC_Type NRF_NVMC_regs;
 #undef NRF_NVMC_BASE
 #define NRF_NVMC_BASE                     (&NRF_NVMC_regs)
 
+#if defined(NRF53_SERIES)
+extern NRF_DPPIC_Type NRF_DPPI_regs;
+#undef NRF_DPPIC_BASE
+#define NRF_DPPIC_BASE                     (&NRF_DPPI_regs)
+extern NRF_EGU_Type NRF_EGU_regs;
+#undef NRF_EGU0_BASE
+#define NRF_EGU0_BASE                     (&NRF_EGU_regs)
+#endif //NRF53_SERIES
+
+
+#undef NRF_FICR
+#undef NRF_UICR
+#undef NRF_BPROT
+#undef NRF_POWER
+#undef NRF_CLOCK
+#undef NRF_RADIO
+#undef NRF_UARTE0
+#undef NRF_UART0
+#undef NRF_SPIM0
+#undef NRF_SPIS0
+#undef NRF_TWIM0
+#undef NRF_TWIS0
+#undef NRF_SPI0
+#undef NRF_TWI0
+#undef NRF_SPIM1
+#undef NRF_SPIS1
+#undef NRF_TWIM1
+#undef NRF_TWIS1
+#undef NRF_SPI1
+#undef NRF_TWI1
+#undef NRF_NFCT
+#undef NRF_GPIOTE
+#undef NRF_SAADC
+#undef NRF_TIMER0
+#undef NRF_TIMER1
+#undef NRF_TIMER2
+#undef NRF_RTC0
+#undef NRF_TEMP
+#undef NRF_RNG
+#undef NRF_ECB
+#undef NRF_CCM
+#undef NRF_AAR
+#undef NRF_WDT
+#undef NRF_RTC1
+#undef NRF_QDEC
+#undef NRF_COMP
+#undef NRF_LPCOMP
+#undef NRF_SWI0
+#undef NRF_EGU0
+#undef NRF_SWI1
+#undef NRF_EGU1
+#undef NRF_SWI2
+#undef NRF_EGU2
+#undef NRF_SWI3
+#undef NRF_EGU3
+#undef NRF_SWI4
+#undef NRF_EGU4
+#undef NRF_SWI5
+#undef NRF_EGU5
+#undef NRF_TIMER3
+#undef NRF_TIMER4
+#undef NRF_PWM0
+#undef NRF_PDM
+#undef NRF_NVMC
+#undef NRF_PPI
+#undef NRF_MWU
+#undef NRF_PWM1
+#undef NRF_PWM2
+#undef NRF_SPIM2
+#undef NRF_SPIS2
+#undef NRF_SPI2
+#undef NRF_RTC2
+#undef NRF_I2S
+#undef NRF_FPU
+#undef NRF_P0
+#undef NRF_DPPIC
+
+
 /*
  * Redefine the peripheral pointers
  */
@@ -143,6 +226,7 @@ extern NRF_NVMC_Type NRF_NVMC_regs;
 #define NRF_I2S                     ((NRF_I2S_Type*)           NRF_I2S_BASE)
 #define NRF_FPU                     ((NRF_FPU_Type*)           NRF_FPU_BASE)
 #define NRF_P0                      ((NRF_GPIO_Type*)          NRF_P0_BASE)
+#define NRF_DPPIC                   ((NRF_DPPIC_Type*)         NRF_DPPIC_BASE)
 
 #ifdef __cplusplus
 }