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[NVPTX] Add TMA Bulk Copy intrinsics (llvm#122344)
PR llvm#96083 added intrinsics for async copy of 'tensor' data using TMA. Following a similar design, this PR adds intrinsics for async copy of bulk data (non-tensor variants) through TMA. * These intrinsics optionally support multicast and cache_hints, as indicated by the boolean arguments at the end of the intrinsics. * The backend looks through these flag arguments and lowers to the appropriate PTX instructions. * Lit tests are added for all combinations of these intrinsics in cp-async-bulk.ll. * The generated PTX is verified with a 12.3 ptxas executable. * Added docs for these intrinsics in NVPTXUsage.rst file. PTX Spec reference: https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk Signed-off-by: Durgadoss R <[email protected]>
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‎llvm/docs/NVPTXUsage.rst‎

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@@ -465,6 +465,94 @@ least-significant bit position. 0xffffffff is returned if no 1 bit is found.
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TMA family of Intrinsics
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------------------------
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'``llvm.nvvm.cp.async.bulk.global.to.shared.cluster``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare void @llvm.nvvm.cp.async.bulk.global.to.shared.cluster(ptr addrspace(3) %dst, ptr addrspace(3) %mbar, ptr addrspace(1) %src, i32 %size, i16 %mc, i64 %ch, i1 %flag_mc, i1 %flag_ch)
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Overview:
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"""""""""
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The '``@llvm.nvvm.cp.async.bulk.global.to.shared.cluster``' intrinsic
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corresponds to the ``cp.async.bulk.shared::cluster.global.*`` family
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of PTX instructions. These instructions initiate an asynchronous
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copy of bulk data from global memory to shared::cluster memory.
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The 32-bit operand ``%size`` specifies the amount of memory to be
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copied and it must be a multiple of 16.
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* The last two arguments to these intrinsics are boolean flags
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indicating support for cache_hint and/or multicast modifiers.
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These flag arguments must be compile-time constants. The backend
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looks through these flags and lowers the intrinsics appropriately.
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* The Nth argument (denoted by ``i1 %flag_ch``) when set, indicates
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a valid cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
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variant of the PTX instruction.
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* The [N-1]th argument (denoted by ``i1 %flag_mc``) when set, indicates
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the presence of a multicast mask (``i16 %mc``) and generates the PTX
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instruction with the ``.multicast::cluster`` modifier.
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For more information, refer PTX ISA
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`<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
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'``llvm.nvvm.cp.async.bulk.shared.cta.to.global``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare void @llvm.nvvm.cp.async.bulk.shared.cta.to.global(ptr addrspace(1) %dst, ptr addrspace(3) %src, i32 %size, i64 %ch, i1 %flag_ch)
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Overview:
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"""""""""
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The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.global``' intrinsic
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corresponds to the ``cp.async.bulk.global.shared::cta.*`` set of PTX
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instructions. These instructions initiate an asynchronous copy from
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shared::cta to global memory. The 32-bit operand ``%size`` specifies
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the amount of memory to be copied and it must be a multiple of 16.
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* The last argument to these intrinsics is a boolean flag
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indicating support for cache_hint. This flag argument must
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be a compile-time constant. When set, it indicates a valid
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cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
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variant of the PTX instruction.
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For more information, refer PTX ISA
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`<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
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'``llvm.nvvm.cp.async.bulk.shared.cta.to.cluster``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare void @llvm.nvvm.cp.async.bulk.shared.cta.to.cluster(ptr addrspace(3) %dst, ptr addrspace(3) %mbar, ptr addrspace(3) %src, i32 %size)
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Overview:
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"""""""""
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The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.cluster``' intrinsic
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corresponds to the ``cp.async.bulk.shared::cluster.shared::cta.*``
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PTX instruction. This instruction initiates an asynchronous copy from
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shared::cta to shared::cluster memory. The destination has to be in
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the shared memory of a different CTA within the cluster. The 32-bit
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operand ``%size`` specifies the amount of memory to be copied and
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it must be a multiple of 16.
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For more information, refer PTX ISA
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`<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
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'``llvm.nvvm.cp.async.bulk.tensor.g2s.tile.[1-5]d``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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‎llvm/include/llvm/IR/IntrinsicsNVVM.td‎

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@@ -4980,4 +4980,47 @@ foreach dim = [1, 2, 3, 4, 5] in {
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}
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}
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// Intrinsics for Bulk Copy using TMA (non-tensor)
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// From Global to Shared Cluster
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def int_nvvm_cp_async_bulk_global_to_shared_cluster
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: DefaultAttrsIntrinsic<[],
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[llvm_shared_ptr_ty, // dst_smem_ptr
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llvm_shared_ptr_ty, // mbarrier_ptr
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llvm_global_ptr_ty, // src_gmem_ptr
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llvm_i32_ty, // copy_size
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llvm_i16_ty, // cta_mask
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llvm_i64_ty, // cache_hint
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llvm_i1_ty, // Flag for cta_mask
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llvm_i1_ty], // Flag for cache_hint
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[IntrConvergent, IntrArgMemOnly,
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WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<2>>,
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NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
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NoCapture<ArgIndex<2>>, ImmArg<ArgIndex<6>>,
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ImmArg<ArgIndex<7>>]>;
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// From Shared CTA to Shared Cluster
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def int_nvvm_cp_async_bulk_shared_cta_to_cluster
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: DefaultAttrsIntrinsic<[],
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[llvm_shared_ptr_ty, // dst_smem_ptr
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llvm_shared_ptr_ty, // mbarrier_ptr
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llvm_shared_ptr_ty, // src_smem_ptr
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llvm_i32_ty], // copy_size
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[IntrConvergent, IntrArgMemOnly,
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WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<2>>,
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NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
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NoCapture<ArgIndex<2>>]>;
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// From Shared CTA to Global memory
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def int_nvvm_cp_async_bulk_shared_cta_to_global
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: DefaultAttrsIntrinsic<[],
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[llvm_global_ptr_ty, // dst_gmem_ptr
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llvm_shared_ptr_ty, // src_smem_ptr
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llvm_i32_ty, // copy_size
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llvm_i64_ty, // cache_hint
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llvm_i1_ty], // Flag for cache_hint
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[IntrConvergent, IntrArgMemOnly,
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WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>,
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NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
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ImmArg<ArgIndex<4>>]>;
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} // let TargetPrefix = "nvvm"

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp‎

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@@ -3024,13 +3024,88 @@ void NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorReduceCommon(SDNode *N,
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ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops));
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}
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void NVPTXDAGToDAGISel::SelectCpAsyncBulkS2G(SDNode *N) {
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// We have {Chain, Intrinsic-ID} followed by the actual intrisic args:
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// dst, src, size, cache_hint, cache_hint_flag
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// NumOperands = {Chain, IID} + {Actual intrinsic args}
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// = {2} + {5}
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size_t NumOps = N->getNumOperands();
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bool IsCacheHint = N->getConstantOperandVal(NumOps - 1) == 1;
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size_t NumArgs = IsCacheHint ? 4 : 3; // src, dst, size, cache_hint
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SDLoc DL(N);
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SmallVector<SDValue, 8> Ops(N->ops().slice(2, NumArgs));
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Ops.push_back(N->getOperand(0)); // Chain operand
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bool IsShared32 =
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CurDAG->getDataLayout().getPointerSizeInBits(ADDRESS_SPACE_SHARED) == 32;
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unsigned Opcode;
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if (IsCacheHint)
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Opcode = IsShared32 ? NVPTX::CP_ASYNC_BULK_S2G_SHARED32_CH
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: NVPTX::CP_ASYNC_BULK_S2G_CH;
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else
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Opcode = IsShared32 ? NVPTX::CP_ASYNC_BULK_S2G_SHARED32
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: NVPTX::CP_ASYNC_BULK_S2G;
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ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops));
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}
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void NVPTXDAGToDAGISel::SelectCpAsyncBulkG2S(SDNode *N) {
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// We have {Chain, Intrinsic-ID} followed by the actual intrisic args:
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// {dst, mbar, src, size, multicast, cache_hint,
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// multicast_flag, cache_hint_flag}
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// NumOperands = {Chain, IID} + {Actual intrinsic args}
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// = {2} + {8}
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size_t NumOps = N->getNumOperands();
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bool IsCacheHint = N->getConstantOperandVal(NumOps - 1) == 1;
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bool IsMultiCast = N->getConstantOperandVal(NumOps - 2) == 1;
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size_t NumBaseArgs = 4; // dst, mbar, src, size
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size_t MultiCastIdx = NumBaseArgs + 2; // for Chain and IID
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SDLoc DL(N);
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SmallVector<SDValue, 8> Ops(N->ops().slice(2, NumBaseArgs));
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// Push MultiCast operand, if available
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if (IsMultiCast)
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Ops.push_back(N->getOperand(MultiCastIdx));
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// Push CacheHint operand, if available
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if (IsCacheHint)
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Ops.push_back(N->getOperand(MultiCastIdx + 1));
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// Finally, the chain operand
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Ops.push_back(N->getOperand(0));
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bool IsShared32 =
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CurDAG->getDataLayout().getPointerSizeInBits(ADDRESS_SPACE_SHARED) == 32;
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unsigned Opcode = [&]() {
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if (IsMultiCast && IsCacheHint)
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return IsShared32 ? NVPTX::CP_ASYNC_BULK_G2S_SHARED32_MC_CH
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: NVPTX::CP_ASYNC_BULK_G2S_MC_CH;
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if (IsMultiCast)
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return IsShared32 ? NVPTX::CP_ASYNC_BULK_G2S_SHARED32_MC
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: NVPTX::CP_ASYNC_BULK_G2S_MC;
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if (IsCacheHint)
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return IsShared32 ? NVPTX::CP_ASYNC_BULK_G2S_SHARED32_CH
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: NVPTX::CP_ASYNC_BULK_G2S_CH;
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return IsShared32 ? NVPTX::CP_ASYNC_BULK_G2S_SHARED32
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: NVPTX::CP_ASYNC_BULK_G2S;
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}();
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ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops));
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}
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bool NVPTXDAGToDAGISel::tryIntrinsicVoid(SDNode *N) {
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unsigned IID = N->getConstantOperandVal(1);
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using TMARedTy = llvm::nvvm::TMAReductionOp;
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auto CastTy = [](TMARedTy Op) { return static_cast<unsigned>(Op); };
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switch (IID) {
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default:
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return false;
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case Intrinsic::nvvm_cp_async_bulk_global_to_shared_cluster:
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SelectCpAsyncBulkG2S(N);
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return true;
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case Intrinsic::nvvm_cp_async_bulk_shared_cta_to_global:
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SelectCpAsyncBulkS2G(N);
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return true;
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case Intrinsic::nvvm_cp_async_bulk_tensor_s2g_tile_1d:
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case Intrinsic::nvvm_cp_async_bulk_tensor_s2g_tile_2d:
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case Intrinsic::nvvm_cp_async_bulk_tensor_s2g_tile_3d:

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h‎

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@@ -90,6 +90,8 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
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bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
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void SelectV2I64toI128(SDNode *N);
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void SelectI128toV2I64(SDNode *N);
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void SelectCpAsyncBulkG2S(SDNode *N);
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void SelectCpAsyncBulkS2G(SDNode *N);
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void SelectCpAsyncBulkTensorG2SCommon(SDNode *N, bool IsIm2Col = false);
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void SelectCpAsyncBulkTensorS2GCommon(SDNode *N, bool IsIm2Col = false);
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void SelectCpAsyncBulkTensorPrefetchCommon(SDNode *N, bool IsIm2Col = false);

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td‎

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@@ -498,9 +498,71 @@ def CP_ASYNC_BULK_WAIT_GROUP_READ :
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[(int_nvvm_cp_async_bulk_wait_group_read timm:$n)]>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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//-----------------------------------
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// TMA Async Tensor Copy Functions
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//-----------------------------------
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//------------------------------
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// TMA Async Bulk Copy Functions
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//------------------------------
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class CpAsyncBulkStr<bit mc, bit ch> {
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// Shared to Global memory
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string S2G = "cp.async.bulk.global.shared::cta.bulk_group"
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# !if(ch, ".L2::cache_hint", "");
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// Global to Shared cluster memory
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string G2S = "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
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# !if(mc, ".multicast::cluster", "")
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# !if(ch, ".L2::cache_hint", "");
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// Shared CTA to Cluster memory
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string C2C = "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes";
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}
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multiclass CP_ASYNC_BULK_S2G<NVPTXRegClass rc> {
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def NAME: NVPTXInst<(outs),
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(ins Int64Regs:$dst, rc:$src, Int32Regs:$size),
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!strconcat(CpAsyncBulkStr<0, 0>.S2G, " [$dst], [$src], $size;"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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def NAME # _CH: NVPTXInst<(outs),
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(ins Int64Regs:$dst, rc:$src, Int32Regs:$size, Int64Regs:$ch),
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!strconcat(CpAsyncBulkStr<0, 1>.S2G, " [$dst], [$src], $size, $ch;"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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}
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defm CP_ASYNC_BULK_S2G : CP_ASYNC_BULK_S2G<Int64Regs>;
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defm CP_ASYNC_BULK_S2G_SHARED32 : CP_ASYNC_BULK_S2G<Int32Regs>;
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multiclass CP_ASYNC_BULK_G2S<NVPTXRegClass rc> {
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def NAME: NVPTXInst<(outs),
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(ins rc:$dst, rc:$mbar, Int64Regs:$src, Int32Regs:$size),
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!strconcat(CpAsyncBulkStr<0, 0>.G2S, " [$dst], [$src], $size, [$mbar];"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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def NAME # _MC: NVPTXInst<(outs),
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(ins rc:$dst, rc:$mbar, Int64Regs:$src, Int32Regs:$size, Int16Regs:$mc),
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!strconcat(CpAsyncBulkStr<1, 0>.G2S, " [$dst], [$src], $size, [$mbar], $mc;"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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def NAME # _CH: NVPTXInst<(outs),
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(ins rc:$dst, rc:$mbar, Int64Regs:$src, Int32Regs:$size, Int64Regs:$ch),
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!strconcat(CpAsyncBulkStr<0, 1>.G2S, " [$dst], [$src], $size, [$mbar], $ch;"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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def NAME # _MC_CH: NVPTXInst<(outs),
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(ins rc:$dst, rc:$mbar, Int64Regs:$src, Int32Regs:$size, Int16Regs:$mc, Int64Regs:$ch),
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!strconcat(CpAsyncBulkStr<1, 1>.G2S, " [$dst], [$src], $size, [$mbar], $mc, $ch;"), []>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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}
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defm CP_ASYNC_BULK_G2S : CP_ASYNC_BULK_G2S<Int64Regs>;
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defm CP_ASYNC_BULK_G2S_SHARED32 : CP_ASYNC_BULK_G2S<Int32Regs>;
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multiclass CP_ASYNC_BULK_CTA_TO_CLUSTER<NVPTXRegClass rc> {
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def NAME: NVPTXInst<(outs),
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(ins rc:$dst, rc:$mbar, rc:$src, Int32Regs:$size),
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!strconcat(CpAsyncBulkStr<0, 0>.C2C, " [$dst], [$src], $size, [$mbar];"),
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[(int_nvvm_cp_async_bulk_shared_cta_to_cluster rc:$dst, rc:$mbar, rc:$src, Int32Regs:$size)]>,
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Requires<[hasPTX<80>, hasSM<90>]>;
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}
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defm CP_ASYNC_BULK_CTA_TO_CLUSTER : CP_ASYNC_BULK_CTA_TO_CLUSTER<Int64Regs>;
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defm CP_ASYNC_BULK_CTA_TO_CLUSTER_SHARED32 : CP_ASYNC_BULK_CTA_TO_CLUSTER<Int32Regs>;
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//-------------------------------------
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// TMA Async Bulk Tensor Copy Functions
565+
//-------------------------------------
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505567
// From Global to Shared memory (G2S)
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class G2S_STRINGS<int dim, string mode, bit mc, bit ch, bit is_shared32 = 0> {

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