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RicePersonRicePerson
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Lab Report
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‎ARM-Lab/reports/Lab06/Lab6_Ford.docx‎

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‎ARM-Lab/reports/Lab06/Lab6_Ford.pdf‎

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‎ARM-Lab/reports/Lab06/iDecode ER Table.png‎

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‎ARM-Lab/reports/Lab06/iDecode ER Table.xlsx‎

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‎ARM-Lab/reports/Lab06/iDecode Results Waveform.png‎

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‎ARM-Lab/tables/Lab6_ExpectedResultsTable.xlsx‎

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‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/iDecode_test_behav.wdb‎

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‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/simulate.log‎

Lines changed: 47 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,4 +91,50 @@ Test Case 7: | B 64
9191
+++ Step 7: Pass: |mem_to_reg| time = 67 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
9292
+++ Step 8: Pass: |alu_op| time = 67 ns | er = 0 | ar = 0 | er_bits = 2 | ar_bits = 2 +++
9393
+++ Step 9: Pass: |mem_write| time = 67 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
94-
+++ Step 10: Pass: |alu_src| time = 67 ns | er = 0 | ar =
94+
+++ Step 10: Pass: |alu_src| time = 67 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
95+
+++ Step 11: Pass: |reg_write| time = 67 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
96+
Test Case 8: | B -55
97+
+++ Step 1: Pass: |opcode| time = 77 ns | er = 10111111 | ar = 10111111 | er_bits = 11 | ar_bits = 11 +++
98+
+++ Step 2: Pass: |sign_extended_output| time = 77 ns | er = ffffffffffffffc9 | ar = ffffffffffffffc9 | er_bits = 64 | ar_bits = 64 +++
99+
+++ Step 3: Pass: |reg2_loc| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
100+
+++ Step 4: Pass: |uncondbranch| time = 77 ns | er = 1 | ar = 1 | er_bits = 1 | ar_bits = 1 +++
101+
+++ Step 5: Pass: |branch| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
102+
+++ Step 6: Pass: |mem_read| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
103+
+++ Step 7: Pass: |mem_to_reg| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
104+
+++ Step 8: Pass: |alu_op| time = 77 ns | er = 0 | ar = 0 | er_bits = 2 | ar_bits = 2 +++
105+
+++ Step 9: Pass: |mem_write| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
106+
+++ Step 10: Pass: |alu_src| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
107+
+++ Step 11: Pass: |reg_write| time = 77 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
108+
Test Case 9: | ORR X9, X10, X21
109+
+++ Step 1: Pass: |opcode| time = 87 ns | er = 10101010000 | ar = 10101010000 | er_bits = 11 | ar_bits = 11 +++
110+
+++ Step 2: Pass: |reg2_loc| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
111+
+++ Step 3: Pass: |uncondbranch| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
112+
+++ Step 4: Pass: |branch| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
113+
+++ Step 5: Pass: |mem_read| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
114+
+++ Step 6: Pass: |mem_to_reg| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
115+
+++ Step 7: Pass: |alu_op| time = 87 ns | er = 10 | ar = 10 | er_bits = 2 | ar_bits = 2 +++
116+
+++ Step 8: Pass: |mem_write| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
117+
+++ Step 9: Pass: |alu_src| time = 87 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
118+
+++ Step 10: Pass: |reg_write| time = 87 ns | er = 1 | ar = 1 | er_bits = 1 | ar_bits = 1 +++
119+
+++ Step 11: Pass: |read_data1| time = 87 ns | er = 30 | ar = 30 | er_bits = 64 | ar_bits = 64 +++
120+
+++ Step 12: Pass: |read_data2| time = 87 ns | er = 0 | ar = 0 | er_bits = 64 | ar_bits = 64 +++
121+
Test Case 10: | AND X9, X22, X10
122+
+++ Step 1: Pass: |opcode| time = 97 ns | er = 10001011000 | ar = 10001011000 | er_bits = 11 | ar_bits = 11 +++
123+
+++ Step 2: Pass: |reg2_loc| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
124+
+++ Step 3: Pass: |uncondbranch| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
125+
+++ Step 4: Pass: |branch| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
126+
+++ Step 5: Pass: |mem_read| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
127+
+++ Step 6: Pass: |mem_to_reg| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
128+
+++ Step 7: Pass: |alu_op| time = 97 ns | er = 10 | ar = 10 | er_bits = 2 | ar_bits = 2 +++
129+
+++ Step 8: Pass: |mem_write| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
130+
+++ Step 9: Pass: |alu_src| time = 97 ns | er = 0 | ar = 0 | er_bits = 1 | ar_bits = 1 +++
131+
+++ Step 10: Pass: |reg_write| time = 97 ns | er = 1 | ar = 1 | er_bits = 1 | ar_bits = 1 +++
132+
+++ Step 11: Pass: |read_data1| time = 97 ns | er = 16 | ar = 16 | er_bits = 64 | ar_bits = 64 +++
133+
+++ Step 12: Pass: |read_data2| time = 97 ns | er = 30 | ar = 30 | er_bits = 64 | ar_bits = 64 +++
134+
135+
Pass Count = 119
136+
Fail Count = 0
137+
138+
******* END TEST RESULTS *******
139+
140+
$finish called at time : 105 ns : File "C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv" Line 389

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/iDecode_test_behav/xsimSettings.ini‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true
2828
SCOPE_NAME_COLUMN_WIDTH=75
2929
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
3030
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
31-
OBJECT_NAME_COLUMN_WIDTH=206
32-
OBJECT_VALUE_COLUMN_WIDTH=146
31+
OBJECT_NAME_COLUMN_WIDTH=75
32+
OBJECT_VALUE_COLUMN_WIDTH=75
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OBJECT_DATA_TYPE_COLUMN_WIDTH=75
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PROCESS_NAME_COLUMN_WIDTH=75
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PROCESS_TYPE_COLUMN_WIDTH=75
@@ -49,37 +49,37 @@ INTERNAL_LOCAL_FILTER=1
4949
CONSTANT_LOCAL_FILTER=1
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VARIABLE_LOCAL_FILTER=1
5151
[Object Radixes]
52-
RADIX_0=unsigned /iDecode_test/iD/read_data1;
53-
RADIX_1=bin /iDecode_test/iD/opcode_wire;
54-
RADIX_2=unsigned /iDecode_test/iD/X_REG/rmem[4];
55-
RADIX_3=unsigned /iDecode_test/iD/X_REG/rmem[16];
56-
RADIX_4=unsigned /iDecode_test/iD/X_REG/rmem[0];
57-
RADIX_5=unsigned /iDecode_test/iD/X_REG/rmem[6];
58-
RADIX_6=unsigned /iDecode_test/iD/X_REG/rmem[3];
59-
RADIX_7=unsigned /iDecode_test/iD/X_REG/rmem[31];
60-
RADIX_8=unsigned /iDecode_test/iD/X_REG/rmem[22];
61-
RADIX_9=unsigned /iDecode_test/iD/X_REG/rmem[8];
62-
RADIX_10=unsigned /iDecode_test/iD/X_REG/rmem[12];
63-
RADIX_11=unsigned /iDecode_test/iD/X_REG/rmem[2];
64-
RADIX_12=unsigned /iDecode_test/iD/X_REG/rmem[11];
65-
RADIX_13=unsigned /iDecode_test/iD/X_REG/rmem[5];
66-
RADIX_14=unsigned /iDecode_test/iD/X_REG/rmem[20];
67-
RADIX_15=unsigned /iDecode_test/iD/X_REG/rmem[13];
68-
RADIX_16=unsigned /iDecode_test/iD/X_REG/rmem[28];
69-
RADIX_17=unsigned /iDecode_test/iD/X_REG/rmem[27];
70-
RADIX_18=unsigned /iDecode_test/iD/X_REG/rmem[25];
71-
RADIX_19=unsigned /iDecode_test/iD/X_REG/rmem[7];
72-
RADIX_20=unsigned /iDecode_test/iD/X_REG/rmem[15];
73-
RADIX_21=unsigned /iDecode_test/iD/X_REG/rmem[29];
74-
RADIX_22=unsigned /iDecode_test/iD/X_REG/rmem[10];
75-
RADIX_23=unsigned /iDecode_test/iD/X_REG/rmem[9];
76-
RADIX_24=unsigned /iDecode_test/iD/X_REG/rmem[14];
77-
RADIX_25=unsigned /iDecode_test/iD/X_REG/rmem[24];
78-
RADIX_26=unsigned /iDecode_test/iD/X_REG/rmem[19];
79-
RADIX_27=unsigned /iDecode_test/iD/X_REG/rmem[21];
80-
RADIX_28=unsigned /iDecode_test/iD/X_REG/rmem[23];
81-
RADIX_29=unsigned /iDecode_test/iD/X_REG/rmem[17];
82-
RADIX_30=unsigned /iDecode_test/iD/X_REG/rmem[26];
83-
RADIX_31=unsigned /iDecode_test/iD/X_REG/rmem[18];
84-
RADIX_32=unsigned /iDecode_test/iD/X_REG/rmem[30];
85-
RADIX_33=unsigned /iDecode_test/iD/X_REG/rmem[1];
52+
RADIX_0=bin /iDecode_test/iD/opcode_wire;
53+
RADIX_1=unsigned /iDecode_test/iD/read_data1;
54+
RADIX_2=unsigned /iDecode_test/iD/X_REG/rmem[6];
55+
RADIX_3=unsigned /iDecode_test/iD/X_REG/rmem[22];
56+
RADIX_4=unsigned /iDecode_test/iD/X_REG/rmem[12];
57+
RADIX_5=unsigned /iDecode_test/iD/X_REG/rmem[0];
58+
RADIX_6=unsigned /iDecode_test/iD/X_REG/rmem[31];
59+
RADIX_7=unsigned /iDecode_test/iD/X_REG/rmem[4];
60+
RADIX_8=unsigned /iDecode_test/iD/X_REG/rmem[16];
61+
RADIX_9=unsigned /iDecode_test/iD/X_REG/rmem[3];
62+
RADIX_10=unsigned /iDecode_test/iD/X_REG/rmem[8];
63+
RADIX_11=unsigned /iDecode_test/iD/X_REG/rmem[19];
64+
RADIX_12=unsigned /iDecode_test/iD/X_REG/rmem[28];
65+
RADIX_13=unsigned /iDecode_test/iD/X_REG/rmem[18];
66+
RADIX_14=unsigned /iDecode_test/iD/X_REG/rmem[30];
67+
RADIX_15=unsigned /iDecode_test/iD/X_REG/rmem[15];
68+
RADIX_16=unsigned /iDecode_test/iD/X_REG/rmem[10];
69+
RADIX_17=unsigned /iDecode_test/iD/X_REG/rmem[9];
70+
RADIX_18=unsigned /iDecode_test/iD/X_REG/rmem[24];
71+
RADIX_19=unsigned /iDecode_test/iD/X_REG/rmem[2];
72+
RADIX_20=unsigned /iDecode_test/iD/X_REG/rmem[5];
73+
RADIX_21=unsigned /iDecode_test/iD/X_REG/rmem[21];
74+
RADIX_22=unsigned /iDecode_test/iD/X_REG/rmem[20];
75+
RADIX_23=unsigned /iDecode_test/iD/X_REG/rmem[11];
76+
RADIX_24=unsigned /iDecode_test/iD/X_REG/rmem[7];
77+
RADIX_25=unsigned /iDecode_test/iD/X_REG/rmem[17];
78+
RADIX_26=unsigned /iDecode_test/iD/X_REG/rmem[1];
79+
RADIX_27=unsigned /iDecode_test/iD/X_REG/rmem[23];
80+
RADIX_28=unsigned /iDecode_test/iD/X_REG/rmem[13];
81+
RADIX_29=unsigned /iDecode_test/iD/X_REG/rmem[27];
82+
RADIX_30=unsigned /iDecode_test/iD/X_REG/rmem[29];
83+
RADIX_31=unsigned /iDecode_test/iD/X_REG/rmem[14];
84+
RADIX_32=unsigned /iDecode_test/iD/X_REG/rmem[26];
85+
RADIX_33=unsigned /iDecode_test/iD/X_REG/rmem[25];

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/iDecode_test_behav/xsimkernel.log‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,3 +2,6 @@ Running: xsim.dir/iDecode_test_behav/xsimk.exe -simmode gui -wdb iDecode_test_be
22
Design successfully loaded
33
Design Loading Memory Usage: 7896 KB (Peak: 7896 KB)
44
Design Loading CPU Usage: 0 ms
5+
Simulation completed
6+
Simulation Memory Usage: 9932 KB (Peak: 9932 KB)
7+
Simulation CPU Usage: 0 ms

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