Closed vivado

Author: BaylorRice

ARM-Lab/code/division.sv

@@ -51,6 +51,7 @@ module division;
     wire clk;
     reg reset;
     reg pc_src;
+
     reg [`WORD-1:0] branch_target;
     wire [`WORD-1:0] cur_pc;
     wire [`INSTR_LEN-1:0] instruction;
@@ -149,12 +150,12 @@ module division;
         .alu_result(alu_result),
         .zero(zero)
     );
-    
-    
+
+
     // iMemory
     wire data_clk;
     wire [`WORD-1:0] mem_read_data;
-    
+
     reg [`WORD - 1:0] er_mem_read_data;
     reg er_pc_src;
 
@@ -170,11 +171,11 @@ module division;
         .mem_read_data(mem_read_data),
         .pc_src(pc_src)
     );
-    
-    
+
+
     // iWriteBack
     reg [`WORD:1-0] er_write_data;
-    
+
     iWriteBack myWriteBack(
         .mem_to_reg(mem_to_reg),
         .read_data(mem_read_data),
@@ -198,7 +199,7 @@ module division;
         .a(clk),
         .a_delayed(write_clk)
     );
-    
+
     delay #(3) clk_delay_data(
         .a(clk),
         .a_delayed(data_clk)
@@ -220,24 +221,25 @@ module division;
     initial
     begin
 
-    begin_test();
-
-    // set reset to 1 to make sure that the PC doesn't increment on the first positive clock edge, 
-    // then set it back to 0 after that first positive clock edge
-    reset = 1;
-    #`CYCLE;
-    reset = 0;
-    
-    // DIVIDE TEST
-    $display("Test Case %0d: | DIVIDE 57/8", tc++);
-    ts = 1;
-    
-    er_read_data2 = 7;
-    
-    #335;
-    verify(ts++, read_data2_string, er_read_data2, $bits(er_read_data2), read_data2, $bits(read_data2), `S_DEC);
-    
-    final_result();
+        begin_test();
+
+
+        // set reset to 1 to make sure that the PC doesn't increment on the first positive clock edge, 
+        // then set it back to 0 after that first positive clock edge
+        reset = 1;
+        #`CYCLE;
+        reset = 0;
+
+        // DIVIDE TEST
+        $display("Test Case %0d: | DIVIDE 56/8", tc++);
+        ts = 1;
+
+        er_read_data2 = 7;
+
+        #335;
+        verify(ts++, read_data2_string, er_read_data2, $bits(er_read_data2), read_data2, $bits(read_data2), `S_DEC);
+
+        final_result();
 
         $finish;
     end

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/compile.bat

@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Tue Apr 23 16:26:26 -0500 2024
+REM Generated by Vivado on Tue Apr 23 16:29:42 -0500 2024
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/division_behav.wdb

@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Tue Apr 23 16:26:28 -0500 2024
+REM Generated by Vivado on Tue Apr 23 16:29:44 -0500 2024
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/elaborate.bat

@@ -0,0 +1,13 @@
+Time resolution is 1 ps
+
+******* BEGIN TEST RESULTS *******
+
+Test Case 1: | DIVIDE 56/8
++++ Step 1: Pass: |read_data2| time = 345 ns | er = 7 | ar = 7 | er_bits = 64 | ar_bits = 64 +++
+
+Pass Count = 1
+Fail Count = 0
+
+******* END TEST RESULTS *******
+
+$finish called at time : 345 ns : File "C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/division.sv" Line 244

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/simulate.log

@@ -148,7 +148,7 @@ void sensitize(char *dp)
 
 void simulate(char *dp)
 {
-iki_register_root_pointers(22, 22552, -5,0,22736, -5,0,22920, -5,0,15872, -5,0,16792, -5,0,15320, -5,0,16240, -5,0,16424, -5,0,16976, -5,0,17160, -5,0,15688, -5,0,15504, -5,0,17344, -5,0,17528, -5,0,13832, -5,0,17712, -5,0,17896, -5,0,16056, -5,0,18080, -5,0,18264, -5,0,16608, -5,0,18448, -5,0) ; 
+iki_register_root_pointers(22, 22736, -5,0,22552, -5,0,22920, -5,0,16240, -5,0,16976, -5,0,18264, -5,0,17896, -5,0,17528, -5,0,18448, -5,0,16792, -5,0,18080, -5,0,16608, -5,0,16424, -5,0,17344, -5,0,17160, -5,0,17712, -5,0,15504, -5,0,15688, -5,0,15320, -5,0,15872, -5,0,16056, -5,0,13832, -5,0) ; 
 		iki_schedule_processes_at_time_zero(dp, "xsim.dir/division_behav/xsim.reloc");
 	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
 	iki_execute_processes();