Skip to content
This repository was archived by the owner on May 8, 2024. It is now read-only.

Commit 8f1d63b

Browse files
BaylorRiceBaylorRice
committed
Closed Vivado
1 parent 6d1f625 commit 8f1d63b

File tree

9 files changed

+4010
-143
lines changed

9 files changed

+4010
-143
lines changed

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/datapath_behav.wdb‎

3.79 KB
Binary file not shown.

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/simulate.log‎

Lines changed: 196 additions & 0 deletions
Large diffs are not rendered by default.

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/datapath_behav/xsimSettings.ini‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -31,14 +31,14 @@ SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
3131
OBJECT_NAME_COLUMN_WIDTH=75
3232
OBJECT_VALUE_COLUMN_WIDTH=75
3333
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
34-
PROCESS_NAME_COLUMN_WIDTH=0
35-
PROCESS_TYPE_COLUMN_WIDTH=0
36-
FRAME_INDEX_COLUMN_WIDTH=0
37-
FRAME_NAME_COLUMN_WIDTH=0
38-
FRAME_FILE_NAME_COLUMN_WIDTH=0
39-
FRAME_LINE_NUM_COLUMN_WIDTH=0
40-
LOCAL_NAME_COLUMN_WIDTH=0
41-
LOCAL_VALUE_COLUMN_WIDTH=0
34+
PROCESS_NAME_COLUMN_WIDTH=75
35+
PROCESS_TYPE_COLUMN_WIDTH=75
36+
FRAME_INDEX_COLUMN_WIDTH=75
37+
FRAME_NAME_COLUMN_WIDTH=75
38+
FRAME_FILE_NAME_COLUMN_WIDTH=75
39+
FRAME_LINE_NUM_COLUMN_WIDTH=75
40+
LOCAL_NAME_COLUMN_WIDTH=134
41+
LOCAL_VALUE_COLUMN_WIDTH=75
4242
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
4343
PROTO_NAME_COLUMN_WIDTH=0
4444
PROTO_VALUE_COLUMN_WIDTH=0

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/datapath_behav/xsimkernel.log‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,3 +2,6 @@ Running: xsim.dir/datapath_behav/xsimk.exe -simmode gui -wdb datapath_behav.wdb
22
Design successfully loaded
33
Design Loading Memory Usage: 7248 KB (Peak: 7248 KB)
44
Design Loading CPU Usage: 62 ms
5+
Simulation completed
6+
Simulation Memory Usage: 9364 KB (Peak: 9364 KB)
7+
Simulation CPU Usage: 78 ms

‎ARM-Project/ARM-Project.xpr‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,7 @@
512512
<Option Name="XSimWcfgFile" Val="$PPRDIR/fde_integration_behav.wcfg"/>
513513
<Option Name="XSimWcfgFile" Val="$PPRDIR/iMemory_test_behav.wcfg"/>
514514
<Option Name="XSimWcfgFile" Val="$PPRDIR/datapath_behav.wcfg"/>
515+
<Option Name="XSimWcfgFile" Val="$PPRDIR/datapath_behav.wcfg"/>
515516
</Config>
516517
</FileSet>
517518
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">

‎ARM-Project/datapath_behav.wcfg‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,15 +12,15 @@
1212
</db_ref>
1313
</db_ref_list>
1414
<zoom_setting>
15-
<ZoomStartTime time="99,998 ps"></ZoomStartTime>
16-
<ZoomEndTime time="100,006 ps"></ZoomEndTime>
17-
<Cursor1Time time="100,000 ps"></Cursor1Time>
15+
<ZoomStartTime time="88.334 ns"></ZoomStartTime>
16+
<ZoomEndTime time="120.479 ns"></ZoomEndTime>
17+
<Cursor1Time time="105.000 ns"></Cursor1Time>
1818
</zoom_setting>
1919
<column_width_setting>
2020
<NameColumnWidth column_width="145"></NameColumnWidth>
21-
<ValueColumnWidth column_width="126"></ValueColumnWidth>
21+
<ValueColumnWidth column_width="122"></ValueColumnWidth>
2222
</column_width_setting>
23-
<WVObjectSize size="49" />
23+
<WVObjectSize size="51" />
2424
<wvobject fp_name="/datapath/tc" type="array">
2525
<obj_property name="ElementShortName">tc[31:0]</obj_property>
2626
<obj_property name="ObjectShortName">tc[31:0]</obj_property>
@@ -41,6 +41,10 @@
4141
<obj_property name="ElementShortName">pc_src</obj_property>
4242
<obj_property name="ObjectShortName">pc_src</obj_property>
4343
</wvobject>
44+
<wvobject fp_name="/datapath/pc_src_tmp" type="logic">
45+
<obj_property name="ElementShortName">pc_src_tmp</obj_property>
46+
<obj_property name="ObjectShortName">pc_src_tmp</obj_property>
47+
</wvobject>
4448
<wvobject fp_name="/datapath/branch_target" type="array">
4549
<obj_property name="ElementShortName">branch_target[63:0]</obj_property>
4650
<obj_property name="ObjectShortName">branch_target[63:0]</obj_property>
@@ -213,6 +217,10 @@
213217
<obj_property name="ElementShortName">er_mem_read_data[63:0]</obj_property>
214218
<obj_property name="ObjectShortName">er_mem_read_data[63:0]</obj_property>
215219
</wvobject>
220+
<wvobject fp_name="/datapath/er_pc_src" type="logic">
221+
<obj_property name="ElementShortName">er_pc_src</obj_property>
222+
<obj_property name="ObjectShortName">er_pc_src</obj_property>
223+
</wvobject>
216224
<wvobject fp_name="/datapath/er_write_data" type="array">
217225
<obj_property name="ElementShortName">er_write_data[64:1]</obj_property>
218226
<obj_property name="ObjectShortName">er_write_data[64:1]</obj_property>

‎ARM-Project/vivado.jou‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,92 @@
1313
start_gui
1414
open_project C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/ARM-Project.xpr
1515
update_compile_order -fileset sources_1
16+
set_property top datapath [get_filesets sim_1]
17+
set_property top_lib xil_defaultlib [get_filesets sim_1]
18+
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
19+
set_property source_mgmt_mode None [current_project]
20+
set_property top datapath [current_fileset]
21+
# Re-enabling previously disabled source management mode.
22+
set_property source_mgmt_mode All [current_project]
23+
update_compile_order -fileset sources_1
24+
launch_simulation
25+
launch_simulation
26+
launch_simulation
27+
launch_simulation
28+
launch_simulation
29+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg
30+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg
31+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg
32+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg
33+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg
34+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg
35+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg
36+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg
37+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg
38+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg
39+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fd_integration_behav.wcfg
40+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_test_behav.wcfg
41+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_control_test_behav.wcfg
42+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iExecute_test_behav.wcfg
43+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fde_integration_behav.wcfg
44+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iMemory_test_behav.wcfg
45+
source datapath.tcl
46+
relaunch_sim
47+
save_wave_config {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg}
48+
add_files -fileset sim_1 -norecurse C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg
49+
set_property xsim.view {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fd_integration_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_control_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iExecute_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fde_integration_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iMemory_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg} [get_filesets sim_1]
50+
relaunch_sim
51+
close_sim
52+
launch_simulation
53+
launch_simulation
54+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg
55+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg
56+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg
57+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg
58+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg
59+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg
60+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg
61+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg
62+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg
63+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg
64+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fd_integration_behav.wcfg
65+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_test_behav.wcfg
66+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_control_test_behav.wcfg
67+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iExecute_test_behav.wcfg
68+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fde_integration_behav.wcfg
69+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iMemory_test_behav.wcfg
70+
open_wave_config C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg
71+
source datapath.tcl
72+
relaunch_sim
73+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 291
74+
relaunch_sim
75+
relaunch_sim
76+
relaunch_sim
77+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 291
78+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 348
79+
relaunch_sim
80+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 295
81+
relaunch_sim
82+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 295
83+
relaunch_sim
84+
relaunch_sim
85+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 348
86+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 394
87+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 394
88+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 405
89+
relaunch_sim
90+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 405
91+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 452
92+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 452
93+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 405
94+
relaunch_sim
95+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 405
96+
add_bp {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} 519
97+
relaunch_sim
98+
remove_bps -file {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/5_writeback/datapath.sv} -line 519
99+
relaunch_sim
100+
relaunch_sim
101+
save_wave_config {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg}
102+
add_files -fileset sim_1 -norecurse C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg
103+
set_property xsim.view {C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fd_integration_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/alu_control_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iExecute_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/fde_integration_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iMemory_test_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/datapath_behav.wcfg} [get_filesets sim_1]
104+
close_sim

0 commit comments

Comments
 (0)