Finished Lab Report and Closed Vivado

Author: BaylorRice

ARM-Lab/reports/Lab04/Lab4_Ford.docx

@@ -1,4 +1,4 @@
 version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:2427094519
+eof:241934075

ARM-Lab/reports/Lab04/Lab4_Ford.pdf

@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Tue Feb 13 17:28:28 -0600 2024
+REM Generated by Vivado on Tue Feb 13 17:33:08 -0600 2024
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
@@ -15,8 +15,8 @@ REM usage: compile.bat
 REM
 REM ****************************************************************************
 REM compile Verilog/System Verilog design sources
-echo "xvlog --incr --relax -L uvm -prj regfile_test_vlog.prj"
-call xvlog  --incr --relax -L uvm -prj regfile_test_vlog.prj -log xvlog.log
+echo "xvlog --incr --relax -L uvm -prj instr_parse_test_vlog.prj"
+call xvlog  --incr --relax -L uvm -prj instr_parse_test_vlog.prj -log xvlog.log
 call type xvlog.log > compile.log
 if "%errorlevel%"=="1" goto END
 if "%errorlevel%"=="0" goto SUCCESS

ARM-Project/ARM-Project.cache/wt/xsim.wdf

@@ -0,0 +1,6 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/instr_parse.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module instr_parse
+INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/0_common/verification_functions.sv" into library xil_defaultlib
+INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/instr_parse_test.sv" into library xil_defaultlib
+WARNING: [VRFC 10-3264] design element 'verification' is previously defined, ignoring this definition [../../../../../ARM-Lab/code/0_common/verification_functions.sv:3]
+INFO: [VRFC 10-311] analyzing module instr_parse_test

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/compile.bat

@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Tue Feb 13 17:28:30 -0600 2024
+REM Generated by Vivado on Tue Feb 13 17:33:09 -0600 2024
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
@@ -15,8 +15,8 @@ REM usage: elaborate.bat
 REM
 REM ****************************************************************************
 REM elaborate design
-echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot regfile_test_behav xil_defaultlib.regfile_test xil_defaultlib.glbl -log elaborate.log"
-call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot regfile_test_behav xil_defaultlib.regfile_test xil_defaultlib.glbl -log elaborate.log
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot instr_parse_test_behav xil_defaultlib.instr_parse_test xil_defaultlib.glbl -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot instr_parse_test_behav xil_defaultlib.instr_parse_test xil_defaultlib.glbl -log elaborate.log
 if "%errorlevel%"=="0" goto SUCCESS
 if "%errorlevel%"=="1" goto END
 :END

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/compile.log

@@ -1,6 +1,6 @@
 Vivado Simulator v2021.2
 Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
-Running: C:/XilinxVitis/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot regfile_test_behav xil_defaultlib.regfile_test xil_defaultlib.glbl -log elaborate.log 
+Running: C:/XilinxVitis/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot instr_parse_test_behav xil_defaultlib.instr_parse_test xil_defaultlib.glbl -log elaborate.log 
 Using 2 slave threads.
 Starting static elaboration
 Pass Through NonSizing Optimizer
@@ -9,9 +9,7 @@ Starting simulation data flow analysis
 Completed simulation data flow analysis
 Time Resolution for simulation is 1ps
 Compiling package xil_defaultlib.verification
-Compiling module xil_defaultlib.oscillator
-Compiling module xil_defaultlib.delay(DELAYAMT=4)
-Compiling module xil_defaultlib.regfile
-Compiling module xil_defaultlib.regfile_test
+Compiling module xil_defaultlib.instr_parse
+Compiling module xil_defaultlib.instr_parse_test
 Compiling module xil_defaultlib.glbl
-Built simulation snapshot regfile_test_behav
+Built simulation snapshot instr_parse_test_behav

ARM-Project/ARM-Project.sim/sim_1/behav/xsim/elaborate.bat

@@ -1,12 +1,10 @@
 # compile verilog/system verilog design source files
 verilog xil_defaultlib  --include "../../../../../ARM-Lab/code/0_common" \
-"../../../../../ARM-Lab/code/0_common/delay.v" \
-"../../../../../ARM-Lab/code/0_common/oscillator.v" \
-"../../../../../ARM-Lab/code/2_decode/regfile.v" \
+"../../../../../ARM-Lab/code/2_decode/instr_parse.v" \
 
 sv xil_defaultlib  --include "../../../../../ARM-Lab/code/0_common" \
 "../../../../../ARM-Lab/code/0_common/verification_functions.sv" \
-"../../../../../ARM-Lab/code/2_decode/regfile_test.sv" \
+"../../../../../ARM-Lab/code/2_decode/instr_parse_test.sv" \
 
 # compile glbl module
 verilog xil_defaultlib "glbl.v"