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‎CPU Visual Simulator.jar‎

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‎README.md‎

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## About
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This CPU Visual Simulator allows you to enter and visualize the execution of assembly language code.
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Instructions and numeric data can be inserted or modified directly in RAM. It is possible to define "labels"
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(identifiers to be used in place of memory addresses) in the greyed table on the left of the RAM: these labels
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can then be used as parameters in jump instructions, or as variable identifiers. At any time, it is possible to
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switch between symbolic and binary representations. It is also possible to directly modify the Program Counter,
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in order to set the next instruction that will be executed.
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![Screenshot](images/screenshot.png?raw=true)
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## How to run
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This Educational CPU Visual Simulator is implemented in Java, and packaged as a single .jar file that you need to download from here.
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In addition to the .jar file, you’ll need the Java Runtime Environment (JRE) to run it. An easy way to find out if you have the JRE already installed, is to double-click the downloaded .jar file:
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if the simulator doesn't start or if you are prompted to select an application to open the file, you might download and install the JRE from Oracle's website - https://www.oracle.com/java/technologies/javase-jre8-downloads.html
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## Instruction set
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#### Data Flow
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| Direct Operand | Immediate Operand | Description |
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|:--------------:|:-----------------:|:------------|
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| LOD X | LOD #X | Load content of Memory Location X (or number #X) into the Accumulator. |
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| STO X | | Store the value of the Accumulator into Memory Location X. |
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#### Control Flow
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| Direct Operand | Immediate Operand | Description |
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|:--------------:|:-----------------:|:------------|
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| JMP P | | Unconditional jump to the instruction at location P. |
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| JZ P | | Jump on Zero: if Flag Z is set, go to instruction number P, otherwise go to the next instruction. |
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| JNZ P | | Jump on Not Zero: if Flag Z is cleared, go to instruction number P, otherwise, go to the next instruction. |
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| JN P | | Jump on Negative: if Flag N is set, go to instruction number P, otherwise go to the next instruction. |
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| JNN P | | Jump on Not Negative: if Flag N is cleared, go to instruction number P, otherwise go to the next instruction. |
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| NOP | | No Operation, go to the next instruction. |
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| HLT | | Halt execution. |
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#### Arithmetic-logic
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| Direct Operand | Immediate Operand | Description |
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|:--------------:|:-----------------:|:------------|
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| ADD X | ADD #X | Add content of Memory Location X (or number #X) to the Accumulator. Flags are updated. |
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| SUB X | SUB #X | Subtract content of Memory Location X (or number #X) from the Accumulator. Flags are updated. |
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| MUL X | MUL #X | Multiply the Accumulator by the content of Memory Location X (or number #X). Flags are updated. |
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| DIV X | DIV #X | Divide the Accumulator by the content of Memory Location X (or number #X). Flags are updated. |
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| AND X | AND #X | Bitwise AND between the Accumulator and the content of Memory Location X (or number #X). Flags are updated. |
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| CMP X | CMP #X | Subtract content of Memory Location X (or number #X) from the Accumulator. Flags are updated, but the content of the Accumulator is not modified. |
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| NOT X | NOT #X | Bitwise NOT of the content of Memory Location X (or number #X). The result is stored in the Accumulator. |
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## Examples
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High level IF-THEN-ELSE example and its translation:
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![IF-THEN-ELSE](images/if-then-else-example.png?raw=true)
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High-level WHILE-DO example and its translation:
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![WHILE-DO](images/while-do-example.png?raw=true)
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## Copyright notice
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Cengage Learning Inc. Reproduced by permission.
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http://www.cengage.com/permissions
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This simulator can be used exclusively for non-commercial, educational activities.
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This CPU Visual Simulator was derived (modified and extended - see credits) in 2021 from the original PIPPIN Applet (© 1998 PWS Publishing Company), with permission from Cengage Learning Inc. Other deletions, additions, edits, changes to, or derivatives of the Cengage Material can only be made with Cengage’s express written approval, email sufficing.
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## Credits
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Original PIPPIN applet:
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* Prof. Stuart Hirshfield and Prof. Rick Decker (Designers)
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CPU Visual Simulator extension, carried out with an Open Pedagogy / OER-enabled process:
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* Renato Cortinovis, PhD - Project coordinator
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* Nicola Preda - Porting to a Java application, initial new functionalities, and documentation
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* Jonathan Cancelli - Implementation of the great majority of new functionalities
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* Alessandro Belotti - Implementation of visualizations and animations
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* Davide Riva - Initial refactoring
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* MariaPia Cavarretta, Giordano Cortinovis, Giovanni Ingargiola, Alessandro Suru, Piero Andrea Sileo and others - Documentation
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Additional information:
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* Cortinovis, R. (2021). An educational CPU Visual Simulator, Proceedings of the 32nd Annual Workshop of the Psychology of Programming Interest Group (PPIG).

‎images/if-then-else-example.png‎

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‎images/screenshot.png‎

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‎images/while-do-example.png‎

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‎src/META-INF/MANIFEST.MF‎

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Manifest-Version: 1.0
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Main-Class: pippin.Main

‎src/pippin/Main.java‎

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/*
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Copyright notice
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Cengage Learning Inc. Reproduced by permission. http://www.cengage.com/permissions
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This simulator can be used exclusively for non-commercial, educational activities.
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This CPU Visual Simulator was derived (modified and extended - see credits) in 2021
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from the original PIPPIN Applet (© 1998 PWS Publishing Company), with permission from
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Cengage Learning Inc. Other deletions, additions, edits, changes to, or derivatives of
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the Cengage Material can only be made with Cengage’s express written approval, email sufficing.
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Credits
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Original PIPPIN applet:
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Prof. Stuart Hirshfield and Prof. Rick Decker (designers)
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CPU Visual Simulator extension, carried out with an Open Pedagogy / OER-enabled process:
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Renato Cortinovis, PhD - project coordinator
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Nicola Preda - porting to a Java application, initial new functionalities, and documentation
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Jonathan Cancelli - implementation of the great majority of new functionalities
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Alessandro Belotti - implementation of visualizations and animations
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Davide Riva - initial refactoring
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MariaPia Cavarretta, Giordano Cortinovis, Giovanni Ingargiola, Alessandro Suru, Piero Andrea Sileo and others - documentation.
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*/
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package pippin;
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import pippin.stage.NEWCPUSim;
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public class Main {
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public static void main(String[] args){
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NEWCPUSim newcpuSim = new NEWCPUSim();
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newcpuSim.setTitle("CPU Visual Simulator");
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newcpuSim.setVisible(true);
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}
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}

‎src/pippin/exceptions/AbortedException.java‎

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/*
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Copyright notice
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Cengage Learning Inc. Reproduced by permission. http://www.cengage.com/permissions
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This simulator can be used exclusively for non-commercial, educational activities.
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This CPU Visual Simulator was derived (modified and extended - see credits) in 2021
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from the original PIPPIN Applet (© 1998 PWS Publishing Company), with permission from
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Cengage Learning Inc. Other deletions, additions, edits, changes to, or derivatives of
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the Cengage Material can only be made with Cengage’s express written approval, email sufficing.
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Credits
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Original PIPPIN applet:
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Prof. Stuart Hirshfield and Prof. Rick Decker (designers)
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CPU Visual Simulator extension, carried out with an Open Pedagogy / OER-enabled process:
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Renato Cortinovis, PhD - project coordinator
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Nicola Preda - porting to a Java application, initial new functionalities, and documentation
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Jonathan Cancelli - implementation of the great majority of new functionalities
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Alessandro Belotti - implementation of visualizations and animations
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Davide Riva - initial refactoring
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MariaPia Cavarretta, Giordano Cortinovis, Giovanni Ingargiola, Alessandro Suru, Piero Andrea Sileo and others - documentation.
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*/
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package pippin.exceptions;
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@SuppressWarnings("serial")
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public class AbortedException extends Exception {
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public AbortedException() {}
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public AbortedException(String s) {
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super(s);
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}
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}

‎src/pippin/resources/images/animate_off.png‎

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‎src/pippin/resources/images/animate_on.png‎

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