|
11 | 11 |
|
12 | 12 |
|
13 | 13 | def compile_board(design: Type[Block], target_dir_name: Optional[Tuple[str, str]]) -> CompiledDesign: |
14 | | - if target_dir_name is not None: |
15 | | - (target_dir, target_name) = target_dir_name |
16 | | - if not os.path.exists(target_dir): |
17 | | - os.makedirs(target_dir) |
18 | | - assert os.path.isdir(target_dir), f"target_dir {target_dir} to compile_board must be directory" |
| 14 | + if target_dir_name is not None: |
| 15 | + (target_dir, target_name) = target_dir_name |
| 16 | + if not os.path.exists(target_dir): |
| 17 | + os.makedirs(target_dir) |
| 18 | + assert os.path.isdir(target_dir), f"target_dir {target_dir} to compile_board must be directory" |
19 | 19 |
|
20 | | - design_filename = os.path.join(target_dir, f'{target_name}.edg') |
21 | | - netlist_filename = os.path.join(target_dir, f'{target_name}.net') |
22 | | - bom_filename = os.path.join(target_dir, f'{target_name}.csv') |
23 | | - svgpcb_filename = os.path.join(target_dir, f'{target_name}.svgpcb.js') |
| 20 | + design_filename = os.path.join(target_dir, f"{target_name}.edg") |
| 21 | + netlist_filename = os.path.join(target_dir, f"{target_name}.net") |
| 22 | + bom_filename = os.path.join(target_dir, f"{target_name}.csv") |
| 23 | + svgpcb_filename = os.path.join(target_dir, f"{target_name}.svgpcb.js") |
24 | 24 |
|
25 | | - with suppress(FileNotFoundError): |
26 | | - os.remove(design_filename) |
27 | | - with suppress(FileNotFoundError): |
28 | | - os.remove(netlist_filename) |
29 | | - with suppress(FileNotFoundError): |
30 | | - os.remove(bom_filename) |
31 | | - with suppress(FileNotFoundError): |
32 | | - os.remove(svgpcb_filename) |
| 25 | + with suppress(FileNotFoundError): |
| 26 | + os.remove(design_filename) |
| 27 | + with suppress(FileNotFoundError): |
| 28 | + os.remove(netlist_filename) |
| 29 | + with suppress(FileNotFoundError): |
| 30 | + os.remove(bom_filename) |
| 31 | + with suppress(FileNotFoundError): |
| 32 | + os.remove(svgpcb_filename) |
33 | 33 |
|
34 | | - compiled = ScalaCompiler.compile(design, ignore_errors=True) |
35 | | - compiled.append_values(RefdesRefinementPass().run(compiled)) |
| 34 | + compiled = ScalaCompiler.compile(design, ignore_errors=True) |
| 35 | + compiled.append_values(RefdesRefinementPass().run(compiled)) |
36 | 36 |
|
37 | | - if target_dir_name is not None: # always dump the proto even if there is an error |
38 | | - with open(design_filename, 'wb') as raw_file: |
39 | | - raw_file.write(compiled.design.SerializeToString()) |
| 37 | + if target_dir_name is not None: # always dump the proto even if there is an error |
| 38 | + with open(design_filename, "wb") as raw_file: |
| 39 | + raw_file.write(compiled.design.SerializeToString()) |
40 | 40 |
|
41 | | - if compiled.errors: |
42 | | - from . import core |
43 | | - raise core.ScalaCompilerInterface.CompilerCheckError(f"error during compilation:\n{compiled.errors_str()}") |
| 41 | + if compiled.errors: |
| 42 | + from . import core |
44 | 43 |
|
45 | | - netlist_all = NetlistBackend().run(compiled) |
46 | | - bom_all = GenerateBom().run(compiled) |
47 | | - svgpcb_all = SvgPcbBackend().run(compiled) |
48 | | - assert len(netlist_all) == 1 |
| 44 | + raise core.ScalaCompilerInterface.CompilerCheckError(f"error during compilation:\n{compiled.errors_str()}") |
49 | 45 |
|
50 | | - if target_dir_name is not None: |
51 | | - with open(netlist_filename, 'w', encoding='utf-8') as net_file: |
52 | | - net_file.write(netlist_all[0][1]) |
| 46 | + netlist_all = NetlistBackend().run(compiled) |
| 47 | + bom_all = GenerateBom().run(compiled) |
| 48 | + svgpcb_all = SvgPcbBackend().run(compiled) |
| 49 | + assert len(netlist_all) == 1 |
53 | 50 |
|
54 | | - with open(bom_filename, 'w', encoding='utf-8') as bom_file: |
55 | | - bom_file.write(bom_all[0][1]) |
| 51 | + if target_dir_name is not None: |
| 52 | + with open(netlist_filename, "w", encoding="utf-8") as net_file: |
| 53 | + net_file.write(netlist_all[0][1]) |
56 | 54 |
|
57 | | - if svgpcb_all: |
58 | | - with open(svgpcb_filename, 'w', encoding='utf-8') as bom_file: |
59 | | - bom_file.write(svgpcb_all[0][1]) |
| 55 | + with open(bom_filename, "w", encoding="utf-8") as bom_file: |
| 56 | + bom_file.write(bom_all[0][1]) |
60 | 57 |
|
61 | | - return compiled |
| 58 | + if svgpcb_all: |
| 59 | + with open(svgpcb_filename, "w", encoding="utf-8") as bom_file: |
| 60 | + bom_file.write(svgpcb_all[0][1]) |
| 61 | + |
| 62 | + return compiled |
62 | 63 |
|
63 | 64 |
|
64 | 65 | def compile_board_inplace(design: Type[Block], generate: bool = True) -> CompiledDesign: |
65 | | - """Compiles a board and writes the results in a sub-directory |
66 | | - where the module containing the top-level is located""" |
67 | | - designfile = inspect.getfile(design) |
68 | | - if generate: |
69 | | - target_dir_name = (os.path.join(os.path.dirname(designfile), design.__name__), design.__name__) |
70 | | - else: |
71 | | - target_dir_name = None |
72 | | - compiled = compile_board(design, target_dir_name) |
73 | | - |
74 | | - return compiled |
| 66 | + """Compiles a board and writes the results in a sub-directory |
| 67 | + where the module containing the top-level is located""" |
| 68 | + designfile = inspect.getfile(design) |
| 69 | + if generate: |
| 70 | + target_dir_name = (os.path.join(os.path.dirname(designfile), design.__name__), design.__name__) |
| 71 | + else: |
| 72 | + target_dir_name = None |
| 73 | + compiled = compile_board(design, target_dir_name) |
| 74 | + |
| 75 | + return compiled |
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