wip

Author: ducky64

edg/jlcparts/JlcPartsBjt.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsBjt(TableBjt, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsBjt(PartsTableSelectorFootprint, JlcPartsBase, TableBjt):
     _JLC_PARTS_FILE_NAMES = ["TransistorsBipolar_Transistors___BJT"]
     _CHANNEL_MAP = {
         'NPN': 'NPN',

edg/jlcparts/JlcPartsDiode.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsDiode(TableDiode, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsDiode(PartsTableSelectorFootprint, JlcPartsBase, TableDiode):
     _JLC_PARTS_FILE_NAMES = [
         "DiodesSchottky_Barrier_Diodes__SBD_",
         "DiodesDiodes___Fast_Recovery_Rectifiers",

edg/jlcparts/JlcPartsElectrolyticCapacitor.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsElectrolyticCapacitor(TableCapacitor, AluminumCapacitor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsElectrolyticCapacitor(PartsTableSelectorFootprint, JlcPartsBase, TableCapacitor, AluminumCapacitor):
     _JLC_PARTS_FILE_NAMES = ["CapacitorsAluminum_Electrolytic_Capacitors___SMD"]
     _PACKAGE_PARSER = re.compile(r"^SMD,D([\d.]+)xL([\d.]+)mm$")
 

edg/jlcparts/JlcPartsFerriteBead.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsFerriteBead(TableFerriteBead, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsFerriteBead(PartsTableSelectorFootprint, JlcPartsBase, TableFerriteBead):
     _JLC_PARTS_FILE_NAMES = ["FiltersakaEMI_OptimizationFerrite_Beads"]
 
     @classmethod

edg/jlcparts/JlcPartsFet.py

@@ -53,11 +53,11 @@ def _entry_to_table_row(cls, row_dict: Dict[PartsTableColumn, Any], filename: st
             return None
 
 
-class JlcPartsFet(TableFet, PartsTableSelectorFootprint, JlcPartsBaseFet):
+class JlcPartsFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableFet):
     pass
 
 
-class JlcPartsSwitchFet(TableSwitchFet, PartsTableSelectorFootprint, JlcPartsBaseFet):
+class JlcPartsSwitchFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableSwitchFet):
     @init_in_parent
     def __init__(self, *args, manual_gate_charge: RangeLike = RangeExpr.ZERO, **kwargs):
         super().__init__(*args, **kwargs)

edg/jlcparts/JlcPartsLed.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsLed(TableLed, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsLed(PartsTableSelectorFootprint, JlcPartsBase, TableLed):
     _JLC_PARTS_FILE_NAMES = [
         "OptoelectronicsLight_Emitting_Diodes__LED_",
         "OptoelectronicsLED_Indication___Discrete",

edg/jlcparts/JlcPartsMlcc.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsMlcc(TableDeratingCapacitor, CeramicCapacitor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsMlcc(PartsTableSelectorFootprint, JlcPartsBase, TableDeratingCapacitor, CeramicCapacitor):
     _JLC_PARTS_FILE_NAMES = ["CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT"]
 
     @init_in_parent
@@ -63,6 +63,15 @@ def filter_minimum_size(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, A
     def _row_sort_by(cls, row: PartsTableRow) -> Any:
         return [row[cls.PARALLEL_COUNT], super(JlcPartsMlcc, cls)._row_sort_by(row)]
 
+    def _row_generate(self, row: PartsTableRow) -> None:
+        # see comment in TableCapacitor._row_generate for why this needs to be here
+        if row[self.PARALLEL_COUNT] == 1:
+            super()._row_generate(row)  # creates the footprint
+        else:
+            TableCapacitor._row_generate(self, row)  # skips creating the footprint in PartsTableSelectorFootprint
+            self.assign(self.actual_basic_part, True)  # dummy value
+            self._make_parallel_footprints(row)
+
     def _make_parallel_footprints(self, row: PartsTableRow) -> None:
         cap_model = JlcDummyCapacitor(set_lcsc_part=row[self.LCSC_COL],
                                       set_basic_part=row[self.BASIC_PART_COL],
@@ -77,8 +86,5 @@ def _make_parallel_footprints(self, row: PartsTableRow) -> None:
             self.connect(self.c[i].pos, self.pos)
             self.connect(self.c[i].neg, self.neg)
 
-        self.assign(self.lcsc_part, row[self.LCSC_COL])
-        self.assign(self.actual_basic_part, row[self.BASIC_PART_COL])
-
 
 lambda: JlcPartsMlcc()  # ensure class is instantiable (non-abstract)

edg/jlcparts/JlcPartsPptcFuse.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsPptcFuse(TableFuse, PptcFuse, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsPptcFuse(PartsTableSelectorFootprint, JlcPartsBase, TableFuse, PptcFuse):
     _JLC_PARTS_FILE_NAMES = ["Circuit_ProtectionResettable_Fuses"]
 
     @classmethod

edg/jlcparts/JlcPartsResistorSmd.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsResistorSmd(TableResistor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsResistorSmd(PartsTableSelectorFootprint, JlcPartsBase, TableResistor):
     _JLC_PARTS_FILE_NAMES = ["ResistorsChip_Resistor___Surface_Mount"]
 
     @classmethod

edg/parts/JlcCapacitor.py

@@ -105,6 +105,7 @@ def _row_sort_by(cls, row: PartsTableRow) -> Any:
     return [row[cls.PARALLEL_COUNT], super(JlcCapacitor, cls)._row_sort_by(row)]
 
   def _row_generate(self, row: PartsTableRow) -> None:
+    # see comment in TableCapacitor._row_generate for why this needs to be here
     if row[self.PARALLEL_COUNT] == 1:
       super()._row_generate(row)  # creates the footprint
     else: