almost there?

Author: ducky64

edg/core/PortBlocks.py

@@ -38,7 +38,7 @@ def Port(self, tpe: T, *args: Any, **kwargs: Any) -> T:
     return super().Port(tpe, *args, optional=True, **kwargs)
 
 
-AdapterDstType = TypeVar('AdapterDstType', bound=Port)
+AdapterDstType = TypeVar('AdapterDstType', covariant=True, bound=Port, default=Port)
 @abstract_block
 class PortAdapter(InternalBlock, Block, Generic[AdapterDstType]):
   """Defines an adapter from one port type to another port type. This behaves as a normal block, and both the src and

edg/electronics_model/CircuitBlock.py

@@ -115,7 +115,7 @@ def contents(self) -> None:
     self.net()
 
 
-AdapterDstType = TypeVar('AdapterDstType', bound='CircuitPort')
+AdapterDstType = TypeVar('AdapterDstType', covariant=True, bound='CircuitPort', default='CircuitPort')
 @abstract_block
 class CircuitPortAdapter(KiCadImportableBlock, NetBaseBlock, PortAdapter[AdapterDstType], Generic[AdapterDstType]):
   def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:

edg/electronics_model/ConnectedGenerator.py

@@ -16,9 +16,9 @@ class DefaultConnectionBlock(InternalBlock):
   pass
 
 
-OutputType = TypeVar('OutputType', bound=Port)
-InputsType = TypeVar('InputsType', bound=Port)
-LinkType = TypeVar('LinkType', bound=Link)
+OutputType = TypeVar('OutputType', covariant=True, bound=Port, default=Port)
+InputsType = TypeVar('InputsType', covariant=True, bound=Port, default=Port)
+LinkType = TypeVar('LinkType', covariant=True, bound=Link, default=Link)
 SelfType = TypeVar('SelfType', bound='BaseConnectedGenerator')
 @non_library  # this can't be instantiated
 class BaseConnectedGenerator(DefaultConnectionBlock, GeneratorBlock, Generic[OutputType, InputsType, LinkType]):

edg/electronics_model/PassivePort.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 
-from typing import TypeVar, Type, Dict
+from typing import TypeVar, Type, Dict, Mapping
 
 from ..core import *
 from .GroundPort import Ground

edg/electronics_model/resources/build_kicad_footprint_table.py

@@ -63,7 +63,7 @@ def polygon_lines_area(lines: List[Line]) -> Optional[float]:
     return abs(sum) / 2
 
 
-def sexp_list_find_all(container: list, key: str) -> List[List[Any]]:
+def sexp_list_find_all(container: list[Any], key: str) -> List[List[Any]]:
     """Given a sexp list, return all elements which are lists where the first element is a symbol of key."""
     matching_elts = []
     for elt in container:

edg/electronics_model/test_kicad_schematic_parser.py

@@ -1,12 +1,12 @@
 import unittest
 
 import os.path
-from typing import Set, Tuple, Type
+from typing import Set, Tuple, Type, Any
 
 from .KiCadSchematicParser import KiCadSchematic, ParsedNet, KiCadGlobalLabel, KiCadLabel, KiCadPowerLabel
 
 
-def net_to_tuple(net: ParsedNet) -> Tuple[Set[Tuple[Type, str]], Set[str]]:
+def net_to_tuple(net: ParsedNet) -> Tuple[Set[Tuple[Type[Any], str]], Set[str]]:
   """Converts a ParsedNet to a tuple of net labels and net pins, so it can be compared during unit testing."""
   labels = set([(x.__class__, x.name) for x in net.labels])
   pins = set([f"{x.refdes}.{x.pin_number}" for x in net.pins])

edg/parts/JlcPart.py

@@ -18,8 +18,8 @@ def __init__(self, *args: Any, require_basic_part: BoolLike = False, **kwargs: A
     self.require(self.require_basic_part.implies(self.actual_basic_part), "required basic part")
 
 
-DescriptionParser = Tuple[re.Pattern,
-                          Callable[[re.Match], Dict[PartsTableColumn, Any]]]
+DescriptionParser = Tuple[re.Pattern[str],
+                          Callable[[re.Match[str]], Dict[PartsTableColumn, Any]]]
 class JlcTableBase(PartsTableBase):
   """Defines common table headers, columns, and functionality for parsing JLCPCB parts tables."""
   PART_NUMBER_COL = 'MFR.Part'  # used only for translation to the PartsTableFootprint col
@@ -63,7 +63,7 @@ def _parse_jlcpcb_common(cls, row: PartsTableRow) -> Dict[PartsTableColumn, Any]
     }
 
   @staticmethod
-  def parse(description: str, regex_dictionary: Dict[str, re.Pattern]) -> Dict[str, str]:
+  def parse(description: str, regex_dictionary: Dict[str, re.Pattern[str]]) -> Dict[str, str]:
     extraction_table = {}
 
     for key, pattern in regex_dictionary.items():

examples/jlcpcb_pcba_postprocess.py

@@ -144,7 +144,7 @@ def remap_by_dict(elt: str, remap_dict: Dict[str, str]) -> str:
     if os.path.exists(f'{args.file_path_prefix}.csv'):  # remove previous one to avoid confusion
       os.remove(f'{args.file_path_prefix}.csv')
     with open(f'{args.file_path_prefix}.csv', 'w', newline='') as bom_out:
-      merged_csv_out: Optional[csv.DictWriter] = None
+      merged_csv_out: Optional[csv.DictWriter[str]] = None
       for input_bom_file in args.merge_boms:
         with open(input_bom_file, 'r', newline='') as bom_in:
           csv_dict_in = csv.DictReader(bom_in)