SMUv3 example (#341)

Another version of the SMU board, that fixes problems with V2.
Specifically:
- Power stage
  - Design target output capability of 30V 3A
  - Bulk Vusb capacitor and input ferrite filter
- Operates off 5v, by using gate drivers that are 4.5v capable and
powered off the buck converter
  - Add comparator / latch protection on Vconv
- Measurement / control stage
  - Use integrated current-sense amp, for greater accuracy and CMRR
- Fixed +33v, -3v analog control rails, to reduce PSRR issues in
measurement
- Use clamping resistors as protection between voltage domains, as
opposed to Zeners
  - Add REF3033 common reference that feeds all references
- Add shielded (coax RX) test points of control and measurement signals
  - Use lower noise opamps, dualpack all the opamps
- Add DUT IO (2 GPIOs) and Qwiic connector (on an independent I2C line)
- Add  2.54mm output option
- Add fan
- Use larger OLED
- Add current ranging (3A / 300mA ranges)
- Move encoder to MCU pins... so it can actually be read by ESPHome

Library improvements:
- Capacitor improvements
  - Add CeramicCapacitor and AluminumCapacitor subtypes
  - Add JlcAluminumCapacitor
- Make TableCapacitor standalone, where auto-parallel-ing and derating
aren't required
  - Add InOut tag to DecouplingCapacitor
- RF connector and test points
  - Add RfConnector base class and UflConnector
- Add RfConnectorTestPoint, for sensitive signals where shielding is
desired
- Add AnalogClampResistor, as protection element for moving signals
between different voltage domains. It changes the modeled voltage range,
but not the signal range; the signal range must be within the output
range.
- Deprecate AnalogClampZenerDiode, it wasn't ever a good option without
a clamping resistor anyways
- Expand inductors footprints and JLC parsing to larger parts
- Add DummyAnalogSource dummy block
- Half Bridge
- Move L/H (independent) and PWM drive to mixins on top of the base
HalfBridgeDriver (gate driver) class and HalfBridge class. PWM enable is
modeled separately via the Resettable mixin
  - Add independent and PWM versions of CustomSyncBuckBoostConverter
  - Add NCP3420 4.5v-compatible gate driver
- Opamps
  - Support schematic-import of OpampFollower
  - Add OPA2171 dual-pack general-purpose 36v opamp
  - Add OPA2189 dual-pack prevision 36v opamp
  - Refactor OPA197/2197 to share common definitions
  - Add TLV9152 dual-pack low-noise 5v amp
- MCP3561: support optional external Vref, generate correct part number
based on used channels
  - No longer possible to export Vref
- Add DG468 analog switch
- Voltage converters
- Fix input and output ripple limits not being propagated in some
devices
  - Add LM2733 boost converter
  - Add LM2664 switched cap inverter
- Misc logic elements
  - Add LMV311 comparator
  - Add SN74LVC1G74 flip-flop with asynchronous (pre)set and reset
- Add Qwiic target connector, that acts as a I2C target (for connecting
Qwiic devices downstream)
  - Add SMT JST-SH connector
- Add AD8418A fixed-gain 20x current sense amp, it should be a lot more
accurate and have less common-mode issues than the discrete diffamp
circuit
- Solid state relays: make the current ratings bidirectional
- Shrink footprint courtyard for SKRH directional switch
- DigitalLink: support the case when only SingleSource and Sink
connected

Infrastructural changes
- Add `RangeExpr.cancel_multiply` and `.center`, to allow
cancel-multiple in expression-land
- Break out StandardFootprint._footprint_pinning_map to allow access to
the pinmaps / supported footprints

Resolves #86 
Resolves #311

Author: ducky64

edg/BoardTop.py

@@ -88,6 +88,7 @@ def refinements(self) -> Refinements:
         (Opamp, Lmv321),
         (SpiMemory, W25q),  # 128M version is a basic part
         (TestPoint, Keystone5015),  # this is larger, but is part of JLC's parts inventory
+        (UflConnector, Bwipx_1_001e),
       ],
       class_values=[  # realistically only RCs are going to likely be basic parts
         (JlcResistor, ['require_basic_part'], True),

edg_core/ConstraintExpr.py

@@ -358,6 +358,15 @@ def _from_lit(cls, pb: edgir.ValueLit) -> Range:
     assert pb.HasField('range') and pb.range.minimum.HasField('floating') and pb.range.maximum.HasField('floating')
     return Range(pb.range.minimum.floating.val, pb.range.maximum.floating.val)
 
+  @classmethod
+  def cancel_multiply(cls, input_side: RangeLike, output_side: RangeLike) -> RangeExpr:
+    """See Range.cancel_multiply"""
+    input_expr = cls._to_expr_type(input_side)
+    output_expr = cls._to_expr_type(output_side)
+    lower = input_expr.upper() * output_expr.lower()
+    upper = input_expr.lower() * output_expr.upper()
+    return cls._to_expr_type((lower, upper))  # rely on internally to check for non-empty range
+
   def __init__(self, initializer: Optional[RangeLike] = None) -> None:
     # must cast non-empty initializer type, because range supports wider initializers
     # TODO and must ignore initializers of self-type (because model weirdness) - remove model support!
@@ -396,6 +405,9 @@ def lower(self) -> FloatExpr:
   def upper(self) -> FloatExpr:
     return self._upper
 
+  def center(self) -> FloatExpr:
+    return (self._lower + self._upper) / 2
+
   @classmethod
   def _create_range_float_binary_op(cls,
                                     lhs: RangeExpr,

electronics_abstract_parts/AbstractCapacitor.py

@@ -84,6 +84,19 @@ def __init__(self, *args, **kwargs) -> None:
     self.neg = self.Port(Passive.empty())
 
 
+@abstract_block
+class CeramicCapacitor(Capacitor):
+  """Abstract base class for ceramic capacitors, which appear more ideal in terms of lower ESP"""
+  pass
+
+
+@abstract_block
+class AluminumCapacitor(Capacitor):
+  """Abstract base class for aluminum electrolytic capacitors capacitors which provide compact bulk capacitance
+  but at the cost of ESR"""
+  pass
+
+
 @non_library
 class CapacitorStandardFootprint(Capacitor, StandardFootprint[Capacitor]):
   REFDES_PREFIX = 'C'
@@ -99,6 +112,56 @@ class CapacitorStandardFootprint(Capacitor, StandardFootprint[Capacitor]):
       'Capacitor_SMD:C_1210_3225Metric',
       'Capacitor_SMD:C_1812_4532Metric',
       'Capacitor_SMD:C_2512_6332Metric',
+
+      'Capacitor_SMD:CP_Elec_3x5.3',
+      'Capacitor_SMD:CP_Elec_3x5.4',
+      'Capacitor_SMD:CP_Elec_4x3',
+      'Capacitor_SMD:CP_Elec_4x3.9',
+      'Capacitor_SMD:CP_Elec_4x4.5',
+      'Capacitor_SMD:CP_Elec_4x5.3',
+      'Capacitor_SMD:CP_Elec_4x5.4',
+      'Capacitor_SMD:CP_Elec_4x5.7',
+      'Capacitor_SMD:CP_Elec_4x5.8',
+      'Capacitor_SMD:CP_Elec_5x3',
+      'Capacitor_SMD:CP_Elec_5x3.9',
+      'Capacitor_SMD:CP_Elec_5x4.4',
+      'Capacitor_SMD:CP_Elec_5x4.5',
+      'Capacitor_SMD:CP_Elec_5x5.3',
+      'Capacitor_SMD:CP_Elec_5x5.4',
+      'Capacitor_SMD:CP_Elec_5x5.7',
+      'Capacitor_SMD:CP_Elec_5x5.8',
+      'Capacitor_SMD:CP_Elec_5x5.9',
+      'Capacitor_SMD:CP_Elec_6.3x3',
+      'Capacitor_SMD:CP_Elec_6.3x3.9',
+      'Capacitor_SMD:CP_Elec_6.3x4.5',
+      'Capacitor_SMD:CP_Elec_6.3x4.9',
+      'Capacitor_SMD:CP_Elec_6.3x5.2',
+      'Capacitor_SMD:CP_Elec_6.3x5.3',
+      'Capacitor_SMD:CP_Elec_6.3x5.4',
+      'Capacitor_SMD:CP_Elec_6.3x5.7',
+      'Capacitor_SMD:CP_Elec_6.3x5.8',
+      'Capacitor_SMD:CP_Elec_6.3x5.9',
+      'Capacitor_SMD:CP_Elec_6.3x7.7',
+      'Capacitor_SMD:CP_Elec_6.3x9.9',
+      'Capacitor_SMD:CP_Elec_8x5.4',
+      'Capacitor_SMD:CP_Elec_8x6.2',
+      'Capacitor_SMD:CP_Elec_8x6.5',
+      'Capacitor_SMD:CP_Elec_8x6.7',
+      'Capacitor_SMD:CP_Elec_8x6.9',
+      'Capacitor_SMD:CP_Elec_8x10',
+      'Capacitor_SMD:CP_Elec_8x10.5',
+      'Capacitor_SMD:CP_Elec_8x11.9',
+      'Capacitor_SMD:CP_Elec_10x7.7',
+      'Capacitor_SMD:CP_Elec_10x7.9',
+      'Capacitor_SMD:CP_Elec_10x10',
+      'Capacitor_SMD:CP_Elec_10x10.5',
+      'Capacitor_SMD:CP_Elec_10x12.5',
+      'Capacitor_SMD:CP_Elec_10x12.6',
+      'Capacitor_SMD:CP_Elec_10x14.3',
+      'Capacitor_SMD:CP_Elec_16x17.5',
+      'Capacitor_SMD:CP_Elec_16x22',
+      'Capacitor_SMD:CP_Elec_18x7.5',
+      'Capacitor_SMD:CP_Elec_18x22',
     ): lambda block: {
       '1': block.pos,
       '2': block.neg,
@@ -121,16 +184,34 @@ class CapacitorStandardFootprint(Capacitor, StandardFootprint[Capacitor]):
 
 
 @non_library
-class TableCapacitor(Capacitor):
-  """Abstract table-based capacitor, providing some interface column definitions.
-  DO NOT USE DIRECTLY - this provides no selection logic implementation."""
+class TableCapacitor(CapacitorStandardFootprint, PartsTableFootprintSelector):
+  """Abstract table-based capacitor, providing some interface column definitions."""
   CAPACITANCE = PartsTableColumn(Range)
   NOMINAL_CAPACITANCE = PartsTableColumn(float)  # nominal capacitance, even with asymmetrical tolerances
   VOLTAGE_RATING = PartsTableColumn(Range)
 
+  @init_in_parent
+  def __init__(self, *args, **kwargs):
+    super().__init__(*args, **kwargs)
+    self.generator_param(self.capacitance, self.voltage, self.voltage_rating_derating, self.exact_capacitance)
+
+  def _row_generate(self, row: PartsTableRow) -> None:
+    super()._row_generate(row)
+    self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
+    self.assign(self.actual_capacitance, row[self.CAPACITANCE])
+
+  def _row_filter(self, row: PartsTableRow) -> bool:
+    derated_voltage = self.get(self.voltage) / self.get(self.voltage_rating_derating)
+    return super()._row_filter(row) and \
+      derated_voltage.fuzzy_in(row[self.VOLTAGE_RATING]) and \
+      self._row_filter_capacitance(row)
+
+  def _row_filter_capacitance(self, row: PartsTableRow) -> bool:
+    return row[self.CAPACITANCE].fuzzy_in(self.get(self.capacitance))
+
 
 @non_library
-class TableDeratingCapacitor(CapacitorStandardFootprint, TableCapacitor, PartsTableFootprintSelector):
+class TableDeratingCapacitor(TableCapacitor):
   """Abstract table-based capacitor with derating based on a part-part voltage coefficient."""
   VOLTCO = PartsTableColumn(float)
   DERATED_CAPACITANCE = PartsTableColumn(Range)
@@ -151,16 +232,13 @@ class TableDeratingCapacitor(CapacitorStandardFootprint, TableCapacitor, PartsTa
   def __init__(self, *args, single_nominal_capacitance: RangeLike = (0, 22)*uFarad, **kwargs):
     super().__init__(*args, **kwargs)
     self.single_nominal_capacitance = self.ArgParameter(single_nominal_capacitance)
-    self.generator_param(self.capacitance, self.voltage, self.single_nominal_capacitance,
-                         self.voltage_rating_derating, self.exact_capacitance)
+    self.generator_param(self.single_nominal_capacitance)
 
     self.actual_derated_capacitance = self.Parameter(RangeExpr())
 
-  def _row_filter(self, row: PartsTableRow) -> bool:
-    derated_voltage = self.get(self.voltage) / self.get(self.voltage_rating_derating)
-    return super()._row_filter(row) and \
-      derated_voltage.fuzzy_in(row[self.VOLTAGE_RATING]) and \
-      Range.exact(row[self.NOMINAL_CAPACITANCE]).fuzzy_in(self.get(self.single_nominal_capacitance))
+  def _row_filter_capacitance(self, row: PartsTableRow) -> bool:
+    # post-derating capacitance filtering is in _table_postprocess
+    return Range.exact(row[self.NOMINAL_CAPACITANCE]).fuzzy_in(self.get(self.single_nominal_capacitance))
 
   def _table_postprocess(self, table: PartsTable) -> PartsTable:
     def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]:
@@ -201,8 +279,6 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
   def _row_generate(self, row: PartsTableRow) -> None:
     if row[self.PARALLEL_COUNT] == 1:
       super()._row_generate(row)  # creates the footprint
-      self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
-      self.assign(self.actual_capacitance, row[self.CAPACITANCE])
       self.assign(self.actual_derated_capacitance, row[self.DERATED_CAPACITANCE])
     else:
       self.assign(self.actual_part, f"{row[self.PARALLEL_COUNT]}x {row[self.PART_NUMBER_COL]}")
@@ -256,7 +332,7 @@ def __init__(self, capacitance: RangeLike, *, exact_capacitance: BoolLike = Fals
     self.pwr = self.Export(self.cap.pos.adapt_to(VoltageSink(
       voltage_limits=(self.cap.actual_voltage_rating + self.gnd.link().voltage).hull(self.gnd.link().voltage),
       current_draw=0*Amp(tol=0)
-    )), [Power])
+    )), [Power, InOut])
 
     self.assign(self.cap.voltage, self.pwr.link().voltage - self.gnd.link().voltage)
 

electronics_abstract_parts/AbstractConnector.py

@@ -14,3 +14,24 @@ def __init__(self) -> None:
 class BananaSafetyJack(BananaJack):
   """Base class for a single terminal 4mm banana jack supporting a safety sheath,
   such as on multimeter leads."""
+
+
+@abstract_block
+class RfConnector(Connector):
+  """Base class for a RF connector, with a signal and ground. Signal is passive-typed."""
+  def __init__(self) -> None:
+    super().__init__()
+    self.sig = self.Port(Passive.empty())
+    self.gnd = self.Port(Ground(), [Common])
+
+
+class RfConnectorTestPoint(BlockInterfaceMixin[RfConnector]):
+  """Test point mixin that allows the footprint to take a name"""
+  @init_in_parent
+  def __init__(self, name: StringLike):
+    super().__init__()
+    self.tp_name = self.ArgParameter(name)
+
+
+class UflConnector(RfConnector):
+  """Base class for a U.FL / IPEX / UMCC connector, miniature RF connector."""

electronics_abstract_parts/AbstractDiodes.py

@@ -1,4 +1,5 @@
 from typing import Dict
+from deprecated import deprecated
 
 from electronics_model import *
 from .DummyDevices import ForcedAnalogVoltage
@@ -183,6 +184,7 @@ def contents(self):
     self.connect(self.diode.anode.adapt_to(Ground()), self.gnd)
 
 
+@deprecated("Use AnalogClampResistor, which should be cheaper and cause less signal distortion")
 class AnalogClampZenerDiode(Protection, KiCadImportableBlock):
   """Analog overvoltage protection diode to clamp the input voltage"""
   @init_in_parent

electronics_abstract_parts/AbstractInductor.py

@@ -64,6 +64,7 @@ class InductorStandardFootprint(Inductor, StandardFootprint[Inductor]):
       'Inductor_SMD:L_Bourns-SRR1005',
       'Inductor_SMD:L_Bourns_SRR1210A',
       'Inductor_SMD:L_Bourns_SRR1260',
+      'Inductor_SMD:L_Bourns_SRP1245A',
 
       'Inductor_SMD:L_Sunlord_SWPA3010S',
       'Inductor_SMD:L_Sunlord_SWPA3012S',
@@ -105,6 +106,14 @@ class InductorStandardFootprint(Inductor, StandardFootprint[Inductor]):
       'Inductor_SMD:L_TDK_SLF12555',
       'Inductor_SMD:L_TDK_SLF12565',
       'Inductor_SMD:L_TDK_SLF12575',
+
+      'Inductor_SMD:L_Vishay_IHLP-1212',
+      'Inductor_SMD:L_Vishay_IHLP-1616',
+      'Inductor_SMD:L_Vishay_IHLP-2020',
+      'Inductor_SMD:L_Vishay_IHLP-2525',
+      'Inductor_SMD:L_Vishay_IHLP-4040',
+      'Inductor_SMD:L_Vishay_IHLP-5050',
+      'Inductor_SMD:L_Vishay_IHLP-6767',
     ): lambda block: {
       '1': block.a,
       '2': block.b,

electronics_abstract_parts/AbstractPowerConverters.py

@@ -373,7 +373,7 @@ def __init__(self, input_voltage: RangeLike, output_voltage: RangeLike, frequenc
                efficiency: RangeLike = (0.8, 1.0),  # from TI reference
                input_voltage_ripple: FloatLike = 75*mVolt,
                output_voltage_ripple: FloatLike = 25*mVolt,
-               dutycycle_limit: RangeLike = (0.2, 0.85)):  # arbitrary
+               dutycycle_limit: RangeLike = (0.1, 0.9)):  # arbitrary
     super().__init__()
 
     self.pwr_in = self.Port(VoltageSink.empty(), [Power])  # models input cap and inductor power draw

electronics_abstract_parts/AbstractResistor.py

@@ -1,5 +1,5 @@
 import re
-from typing import Optional, cast, Mapping
+from typing import Optional, cast, Mapping, Dict
 
 from electronics_model import *
 from .PartsTable import PartsTableColumn, PartsTableRow
@@ -228,7 +228,7 @@ def __init__(self, resistance: RangeLike) -> None:
 
     self.pwr_out = self.Port(VoltageSource.empty(), [Output])  # forward declaration
     self.pwr_in = self.Port(VoltageSink.empty(), [Power, Input])  # forward declaration
-    current_draw = self.pwr_out.link().current_drawn
+    current_draw = self.pwr_out.link().current_drawn.abs()
 
     self.res = self.Block(Resistor(
       resistance=self.resistance,
@@ -293,3 +293,46 @@ def connected(self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optiona
     if pwr_out is not None:
       cast(Block, builder.get_enclosing_block()).connect(pwr_out, self.pwr_out)
     return self
+
+
+class AnalogClampResistor(Protection, KiCadImportableBlock):
+  """Inline resistor that limits the current (to a parameterized amount) which works in concert
+  with ESD diodes in the downstream device to clamp the signal voltage to allowable levels.
+
+  The protection voltage can be extended beyond the modeled range from the input signal,
+  and can also be specified to allow zero output voltage (for when the downstream device
+  is powered down)
+
+  TODO: clamp_target should be inferred from the target voltage_limits,
+  but voltage_limits doesn't always get propagated"""
+  @init_in_parent
+  def __init__(self, clamp_target: RangeLike = (0, 3)*Volt, clamp_current: RangeLike = (0.25, 2.5)*mAmp,
+               protection_voltage: RangeLike = (0, 0)*Volt, zero_out: BoolLike = False):
+    super().__init__()
+
+    self.signal_in = self.Port(AnalogSink.empty(), [Input])
+    self.signal_out = self.Port(AnalogSource.empty(), [Output])
+
+    self.clamp_target = self.ArgParameter(clamp_target)
+    self.clamp_current = self.ArgParameter(clamp_current)
+    self.protection_voltage = self.ArgParameter(protection_voltage)
+    self.zero_out = self.ArgParameter(zero_out)
+
+  def contents(self):
+    super().contents()
+
+    # TODO bidirectional clamping calcs?
+    self.res = self.Block(Resistor(resistance=1/self.clamp_current * self.zero_out.then_else(
+      self.signal_in.link().voltage.hull(self.protection_voltage).upper(),
+      self.signal_in.link().voltage.hull(self.protection_voltage).upper() - self.clamp_target.upper(),
+    )))
+    self.connect(self.res.a.adapt_to(AnalogSink()), self.signal_in)
+    self.connect(self.res.b.adapt_to(AnalogSource(
+      voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target),
+      signal_out=self.signal_in.link().signal,
+      impedance=self.signal_in.link().source_impedance + self.res.actual_resistance
+    )), self.signal_out)
+
+  def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]:
+    assert symbol_name == 'Device:R'
+    return {'1': self.signal_in, '2': self.signal_out}

electronics_abstract_parts/AbstractTestPoint.py

@@ -1,8 +1,10 @@
-from typing import cast, List
+from typing import cast
 
 from electronics_model import *
 from electronics_model.CanPort import CanLogicLink
 from electronics_model.I2cPort import I2cLink
+from .AbstractConnector import RfConnector, RfConnectorTestPoint
+from .AbstractResistor import Resistor
 from .Categories import *
 
 
@@ -32,6 +34,23 @@ def contents(self):
     self.assign(self.tp.tp_name, (self.tp_name == "").then_else(self.io.link().name(), self.tp_name))
 
 
+@non_library
+class BaseRfTestPoint(TypedTestPoint, Block):
+  """Base class with utility infrastructure for typed RF test points."""
+  @init_in_parent
+  def __init__(self, tp_name: StringLike = "") -> None:
+    super().__init__()
+    self.tp_name = self.ArgParameter(tp_name)
+    self.conn = self.Block(RfConnector())
+    self.gnd = self.Export(self.conn.gnd, [Common])
+    self.io: Port
+
+  def contents(self):
+    super().contents()
+    conn_tp = self.conn.with_mixin(RfConnectorTestPoint(StringExpr()))
+    self.assign(conn_tp.tp_name, (self.tp_name == "").then_else(self.io.link().name(), self.tp_name))
+
+
 class VoltageTestPoint(BaseTypedTestPoint, Block):
   """Test point with a VoltageSink port."""
   def __init__(self, *args):
@@ -78,7 +97,7 @@ def generate(self):
 
 
 class AnalogTestPoint(BaseTypedTestPoint, Block):
-  """Test point with a AnalogSink port."""
+  """Test point with a AnalogSink port"""
   def __init__(self, *args):
     super().__init__(*args)
     self.io = self.Port(AnalogSink.empty(), [InOut])
@@ -89,6 +108,19 @@ def connected(self, io: Port[AnalogLink]) -> 'AnalogTestPoint':
     return self
 
 
+class AnalogRfTestPoint(BaseRfTestPoint, Block):
+  """Test point with a AnalogSink port and 50-ohm matching resistor."""
+  def __init__(self, *args):
+    super().__init__(*args)
+    self.res = self.Block(Resistor(50*Ohm(tol=0.05)))
+    self.io = self.Export(self.res.a.adapt_to(AnalogSink()), [InOut])
+    self.connect(self.res.b, self.conn.sig)
+
+  def connected(self, io: Port[AnalogLink]) -> 'AnalogRfTestPoint':
+    cast(Block, builder.get_enclosing_block()).connect(io, self.io)
+    return self
+
+
 class I2cTestPoint(TypedTestPoint, Block):
   """Two test points for I2C SDA and SCL"""
   @init_in_parent