fix

Author: ducky64

edg/core/PortBlocks.py

@@ -1,12 +1,10 @@
 from __future__ import annotations
 
-from typing import *
+from typing import Any, Generic
+from typing_extensions import TypeVar
 
-from .. import edgir
 from .Categories import InternalBlock
-from .Core import Refable
 from .HierarchyBlock import Block, abstract_block
-from .IdentityDict import IdentityDict
 from .Ports import BasePort, Port
 
 

edg/electronics_model/ConnectedGenerator.py

@@ -1,4 +1,5 @@
-from typing import Type, TypeVar, Generic
+from typing import Type, Generic
+from typing_extensions import TypeVar
 
 from ..core import *
 from .VoltagePorts import VoltageLink, VoltageSink, VoltageSource