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Fix for single element designs (#347)
Prevents pruning the top-level path in netlisting. Previously the netlister would prune all the paths and the kicad netlist generator would crash. Also regenerate netlists.
1 parent 74dcedd commit ba1570c

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7 files changed

+1722
-1074
lines changed

7 files changed

+1722
-1074
lines changed

electronics_abstract_parts/test_kicad_import_netlist.py

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -71,16 +71,19 @@ def test_netlist(self):
7171
self.assertIn(NetBlock('Package_TO_SOT_SMD:SOT-23', 'U1',
7272
# expected value is wonky because netlisting combines part and value
7373
'Sensor_Temperature:MCP9700AT-ETT', 'MCP9700AT-ETT',
74-
['dut', 'U1'], ['U1'],
75-
['electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
74+
['dut', 'U1'], ['dut', 'U1'],
75+
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
76+
'electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
7677
net.blocks)
7778
self.assertIn(NetBlock('Symbol:Symbol_ESD-Logo_CopperTop', 'SYM1',
7879
# expected value is wonky because netlisting combines part and value
7980
'Graphic:SYM_ESD_Small', 'SYM_ESD_Small',
80-
['dut', 'SYM1'], ['SYM1'],
81-
['electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
81+
['dut', 'SYM1'], ['dut', 'SYM1'],
82+
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
83+
'electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
8284
net.blocks)
8385
self.assertIn(NetBlock('Resistor_SMD:R_0603_1608Metric', 'R1', '', '',
84-
['dut', 'res'], ['res'],
85-
['electronics_abstract_parts.test_kicad_import_netlist.DummyResistor']),
86+
['dut', 'res'], ['dut', 'res'],
87+
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
88+
'electronics_abstract_parts.test_kicad_import_netlist.DummyResistor']),
8689
net.blocks)

electronics_model/NetlistGenerator.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ def process_blocklike(self, path: TransformUtil.Path, block: Union[edgir.Link, e
7979
short_path = self.short_paths[path]
8080
class_path = self.class_paths[path]
8181

82-
if len(main_internal_blocks) == 1:
82+
if len(main_internal_blocks) == 1 and short_path: # never shorten top-level blocks
8383
name = list(main_internal_blocks.keys())[0]
8484
self.short_paths[path.append_block(name)] = short_path
8585
self.class_paths[path.append_block(name)] = class_path

electronics_model/test_netlist.py

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ class TestFakeSource(FootprintBlock):
2424
def __init__(self) -> None:
2525
super().__init__()
2626

27-
self.pos = self.Port(VoltageSource())
28-
self.neg = self.Port(VoltageSource())
27+
self.pos = self.Port(VoltageSource(), optional=True)
28+
self.neg = self.Port(VoltageSource(), optional=True)
2929

3030
def contents(self) -> None:
3131
super().contents()
@@ -63,6 +63,13 @@ def contents(self) -> None:
6363
)
6464

6565

66+
class TestSinglePart(Block):
67+
def contents(self) -> None:
68+
super().contents()
69+
70+
self.source = self.Block(TestFakeSource())
71+
72+
6673
class TestBasicCircuit(Block):
6774
def contents(self) -> None:
6875
super().contents()
@@ -182,6 +189,14 @@ def generate_net(design: Type[Block], refinements: Refinements = Refinements()):
182189
compiled.append_values(RefdesRefinementPass().run(compiled))
183190
return NetlistTransform(compiled).run()
184191

192+
def test_single_netlist(self) -> None:
193+
net = self.generate_net(TestSinglePart)
194+
195+
# check that the top-level path element is never pruned, even when the design is one element
196+
self.assertIn(NetBlock('Capacitor_SMD:C_0603_1608Metric', 'C1', '', '1uF',
197+
['source'], ['source'],
198+
['electronics_model.test_netlist.TestFakeSource']), net.blocks)
199+
185200
def test_basic_netlist(self) -> None:
186201
net = self.generate_net(TestBasicCircuit)
187202

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