SMU v3.1 (#397)

SMUv3.1 and associated infrastructural changes. Major improvements to
reliability, stability, and (hopefully) resolution (noise floor).
Resolves #351

Changes:
- Change emitter follower to be able to independently control gate on
status on high and low sides
  - Refactor to use positive gate voltage instead of power 
- Rename ErrorAmplifier -> GatedSummingAmplifier to better reflect the
standard topology
  - Improved docs
  - Add optional fine target input
- Add optional sense output, upstream of the gating / resistive output
element (to detect current limiting mode)
rails, for headroom on analog switches
  - Make gate clamping voltage (zener) a parameter
- Add JFET current clamp and simulation
- Refactor SMU control schematic:
  - for readability
  - to be self-contained
  - change current sense amplifier to use inamps
- better output protection with a R-C snubber and low-leakage TVS diodes
- Add S-R inverted latch as SMU only block
- SMU top changes
  - Use TO-220 for pass FETs, which should allow much better heatsinking
  - Add blowy fuse to the USB input
  - Use buck converter for direct Vbus -> 3.3v digital
  - Add INA219 power sense on Vbus input and Vconv in
  - Run Vcontrol- off analog rail, with ferrite filter
  - Add ramp limiter
  - Add current limit trip sense direct to MCU
  - Use RC for OLED reset, because we're out of MCU pins
- Add another IO expander for low-speed controls, because we're _really_
out of MCU pins
  - Use SR with priority for converter OVP - should be more robust
  - Add I2S speaker
  - Simplify HDL using some new libraries
  - Add experimental block diagram grouping directive
- Move SMU schematics into its folder
- Rebaseline netlists
- Delete calibration worksheet for old device

Libraries added:
- Add AnalogCapacitor as a cap to be sprinkled on analog lines.
Apparently this is a thing in analog design.
- Add VoltageComparator, a comparator against a set (absolute) voltage.
- Add base SeriesPowerFuse, for blowy fuses
- Add SeriesResistor generator, that breaks a resistor into a series
combination, to increase power and voltage ratings. Applies derating for
worst-case tolerance stackup for individual voltage and power ratings.
- Add summing amplifier ratio calculator for n-ported noninverting
summing amplifier, with unit test. No block yet.
- Add differential-RC filter
- Add more KiCad symbols to analog signal chain parts: voltage dividers
- Add Nano2 / 154 series fuseholder, with no modeling.
- Add INA826 in-amp
- Add SN74LVC2G02 dual NOR gate
- Add TLP170AM low(er)-cost SSR
- Add TO-220 FETs
- Add Sn74lvc1g3157 analog switch, as the NLAS4157 is obsolete. Higher
on-state resistance.
- Add Ws2812c_2020 0808-size Neopixel LED, which is 3v3 logic
compatible. Adds decoupling capacitors, which will be standard for
Neopixels going forward.

Libraries modified:
- Add mclkin for MCP3561, so we can overclock those ADCs
- Add addr lsb selection on INA219
- Expand Cf target tolerance for Lm2733, to give more flexibility in
capacitance
- Deprecate NLAS4157 (obsoleted part)
- Change Mcp4728 to use the -T part, which is more common.
- Shrink courtyards on non-connector footprints, both for optimization
and to standardize to KiCad's library guidelines.

Fixes to JlcParts:
- Fix require_basic_part in default refinements
- Fix diode parsing
- Expand diode footprint parsing rules

Core changes:
- Add range-float subtraction (in addition to existing float-range
subtraction). Range-range subtraction is still undefined because the
tolerancing is non-intuitive.
- Add Ratio (like kOhm, and nFarad, but for unitless), which cleans up a
lot of cases, resolves #391
- Add as_voltage_source adapter for AnalogSource
- Add KiCad instantiation to SeriesPowerResistor

---------

Co-authored-by: dc37 <[email protected]>

Author: ducky64

edg/abstract_parts/AbstractAnalogSwitch.py

@@ -22,6 +22,7 @@ def __init__(self) -> None:
     self.pwr = self.Port(VoltageSink.empty(), [Power])
     self.gnd = self.Port(Ground.empty(), [Common])
 
+    self.control_gnd = self.Port(Ground.empty(), optional=True)  # optional separate ground for control signal
     self.control = self.Port(Vector(DigitalSink.empty()))  # length source
 
     self.com = self.Port(Passive.empty())
@@ -40,7 +41,7 @@ class AnalogSwitchTree(AnalogSwitch, GeneratorBlock):
   def __init__(self, switch_size: IntLike = 0):
     super().__init__()
     self.switch_size = self.ArgParameter(switch_size)
-    self.generator_param(self.switch_size, self.inputs.requested())
+    self.generator_param(self.switch_size, self.inputs.requested(), self.control_gnd.is_connected())
 
   def generate(self):
     import math
@@ -72,6 +73,8 @@ def generate(self):
         all_switches.append(sw)
         self.connect(sw.pwr, self.pwr)
         self.connect(sw.gnd, self.gnd)
+        if self.get(self.control_gnd.is_connected()):
+            self.connect(sw.control_gnd, self.control_gnd)
 
         for sw_port_i in range(switch_size):
           port_i = sw_i * switch_size + sw_port_i
@@ -115,6 +118,8 @@ def __init__(self) -> None:
     self.device = self.Block(AnalogSwitch())
     self.pwr = self.Export(self.device.pwr, [Power])
     self.gnd = self.Export(self.device.gnd, [Common])
+
+    self.control_gnd = self.Port(Ground.empty(), optional=True)  # optional separate ground for control signal
     self.control = self.Export(self.device.control)
 
     self.inputs = self.Port(Vector(AnalogSink.empty()))
@@ -125,7 +130,7 @@ def __init__(self) -> None:
       impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance)
     )))
 
-    self.generator_param(self.inputs.requested())
+    self.generator_param(self.inputs.requested(), self.control_gnd.is_connected())
 
   def generate(self):
     super().generate()
@@ -138,6 +143,8 @@ def generate(self):
           current_draw=self.out.link().current_drawn,
           impedance=self.out.link().sink_impedance + self.device.analog_on_resistance
         )))
+      if self.get(self.control_gnd.is_connected()):
+        self.connect(self.control_gnd, self.device.control_gnd)
 
   def mux_to(self, inputs: Optional[List[Port[AnalogLink]]] = None,
              output: Optional[Port[AnalogLink]] = None) -> 'AnalogMuxer':

edg/abstract_parts/AbstractCapacitor.py

@@ -336,7 +336,33 @@ def connected(self, gnd: Optional[Port[GroundLink]] = None, pwr: Optional[Port[V
     return self
 
 
-class CombinedCapacitorElement(Capacitor):
+class AnalogCapacitor(DiscreteApplication, KiCadImportableBlock):
+  """Capacitor attached to an analog line, that presents as an open model-wise.
+  """
+  def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:
+    assert symbol_name in ('Device:C', 'Device:C_Small', 'Device:C_Polarized', 'Device:C_Polarized_Small')
+    return {'1': self.io, '2': self.gnd}
+
+  def __init__(self, capacitance: RangeLike, *, exact_capacitance: BoolLike = False) -> None:
+    super().__init__()
+
+    self.cap = self.Block(Capacitor(capacitance, voltage=RangeExpr(), exact_capacitance=exact_capacitance))
+    self.gnd = self.Export(self.cap.neg.adapt_to(Ground()), [Common])
+    self.io = self.Export(self.cap.pos.adapt_to(AnalogSink()), [InOut])  # ideal open port
+
+    self.assign(self.cap.voltage, self.io.link().voltage - self.gnd.link().voltage)
+
+  def connected(self, gnd: Optional[Port[GroundLink]] = None, io: Optional[Port[AnalogLink]] = None) -> \
+          'AnalogCapacitor':
+    """Convenience function to connect both ports, returning this object so it can still be given a name."""
+    if gnd is not None:
+      cast(Block, builder.get_enclosing_block()).connect(gnd, self.gnd)
+    if io is not None:
+      cast(Block, builder.get_enclosing_block()).connect(io, self.io)
+    return self
+
+
+class CombinedCapacitorElement(Capacitor):  # to avoid an abstract part error
   def contents(self):
     super().contents()
     self.assign(self.actual_capacitance, self.capacitance)  # fake it, since a combined capacitance is handwavey

edg/abstract_parts/AbstractComparator.py

@@ -1,5 +1,6 @@
 from typing import Mapping
 
+from .ResistiveDivider import FeedbackVoltageDivider, VoltageDivider
 from ..abstract_parts import Analog
 from ..electronics_model import *
 
@@ -22,3 +23,65 @@ def __init__(self) -> None:
         self.inn = self.Port(AnalogSink.empty())
         self.inp = self.Port(AnalogSink.empty())
         self.out = self.Port(DigitalSource.empty())
+
+
+class VoltageComparator(GeneratorBlock):
+    """A comparator subcircuit that compares an input voltage rail against some reference, either
+    internally generated from the power lines or an external analog signals.
+    Accounts for tolerance stackup on the reference input - so make sure the trip
+    tolerance is specified wide enough.
+    The output is logic high when the input exceeds the trip voltage by default,
+    this can be inverted with the invert parameter.
+    Optionally this can take a reference voltage input, otherwise this generates a divider.
+
+    TODO: maybe a version that takes an input analog signal?
+    """
+    def __init__(self, trip_voltage: RangeLike, *, invert: BoolLike = False,
+                 input_impedance: RangeLike=(4.7, 47)*kOhm,
+                 trip_ref: RangeLike=1.65*Volt(tol=0.10)):
+        super().__init__()
+        self.comp = self.Block(Comparator())
+        self.gnd = self.Export(self.comp.gnd, [Common])
+        self.pwr = self.Export(self.comp.pwr, [Power])
+        self.input = self.Port(AnalogSink.empty(), [Input])
+        self.output = self.Export(self.comp.out, [Output])
+        self.ref = self.Port(AnalogSink.empty(), optional=True)
+
+        self.trip_voltage = self.ArgParameter(trip_voltage)
+        self.invert = self.ArgParameter(invert)
+        self.trip_ref = self.ArgParameter(trip_ref)  # only used if self.ref disconnected
+        self.input_impedance = self.ArgParameter(input_impedance)
+        self.generator_param(self.ref.is_connected(), self.invert)
+
+        self.actual_trip_voltage = self.Parameter(RangeExpr())
+
+    def generate(self):
+        super().generate()
+
+        if self.get(self.ref.is_connected()):
+            ref_pin: Port[AnalogLink] = self.ref
+            ref_voltage = self.ref.link().signal
+        else:
+            self.ref_div = self.Block(VoltageDivider(
+                output_voltage=self.trip_ref,
+                impedance=self.input_impedance,
+            ))
+            self.connect(self.ref_div.input, self.pwr)
+            self.connect(self.ref_div.gnd, self.gnd)
+            ref_pin = self.ref_div.output
+            ref_voltage = self.ref_div.output.link().signal
+
+        self.comp_div = self.Block(FeedbackVoltageDivider(
+            impedance=self.input_impedance,
+            output_voltage=ref_voltage,
+            assumed_input_voltage=self.trip_voltage
+        ))
+        self.assign(self.actual_trip_voltage, self.comp_div.actual_input_voltage)
+        self.connect(self.comp_div.input, self.input.as_voltage_source())
+        self.connect(self.comp_div.gnd, self.gnd)
+        if not self.get(self.invert):  # positive connection
+            self.connect(self.comp.inp, self.comp_div.output)
+            self.connect(self.comp.inn, ref_pin)
+        else:  # negative connection
+            self.connect(self.comp.inn, self.comp_div.output)
+            self.connect(self.comp.inp, ref_pin)

edg/abstract_parts/AbstractFets.py

@@ -48,6 +48,15 @@ class FetStandardFootprint(StandardFootprint['Fet']):
       '4': block.gate,
       '5': block.drain,
     },
+    (
+      'Package_TO_SOT_THT:TO-220-3_Horizontal_TabUp',
+      'Package_TO_SOT_THT:TO-220-3_Horizontal_TabDown',
+      'Package_TO_SOT_THT:TO-220-3_Vertical',
+    ): lambda block: {
+      '1': block.gate,
+      '2': block.drain,
+      '3': block.source,
+    },
   }
 
 

edg/abstract_parts/AbstractResistor.py

@@ -125,6 +125,53 @@ def _row_sort_by(cls, row: PartsTableRow) -> Any:
             super()._row_sort_by(row))
 
 
+class SeriesResistor(Resistor, GeneratorBlock):
+  """Splits a resistor into equal resistors in series. Improves power and voltage ratings
+  by distributing the load across multiple devices.
+
+  Generally used as a refinement to break up a single (logical) resistor that is dissipating too much power
+  or has an excessive voltage across it. Accounts for tolerance stackup for power and voltage distribution
+  using specified (not actual) resistor tolerance - is a pessimistic calculation."""
+  def __init__(self, *args, count: IntLike = 2, **kwargs):
+    super().__init__(*args, **kwargs)
+    self.count = self.ArgParameter(count)
+    self.generator_param(self.count, self.resistance)
+
+  def generate(self):
+    super().generate()
+    count = self.get(self.count)
+    last_port = self.a
+    cumu_resistance: RangeLike = Range.exact(0)
+    cumu_power_rating: RangeLike = Range.exact(0)
+    cumu_voltage_rating: RangeLike = Range.exact(0)
+    self.res = ElementDict[Resistor]()
+
+    # calculate tolerance stackup effects on R for worst-case power and voltage
+    resistance_range = self.get(self.resistance)
+    resistance_tol = (resistance_range.upper - resistance_range.lower) / 2 / resistance_range.center()
+    resistance_tol = min(0.05, resistance_tol)  # in practice there should be no >5% resistors
+    resistance_ratio_range = Range((1 - resistance_tol) / (count + resistance_tol * (count - 2)),
+                                   (1 + resistance_tol) / (count - resistance_tol * (count - 2)))
+
+    elt_resistance = resistance_range / count
+    elt_power = self.power * resistance_ratio_range
+    elt_voltage = self.voltage * resistance_ratio_range
+
+    for i in range(count):
+      self.res[i] = res = self.Block(Resistor(resistance=elt_resistance,
+                                              power=elt_power,
+                                              voltage=elt_voltage))
+      self.connect(last_port, res.a)
+      cumu_resistance = cumu_resistance + res.actual_resistance
+      cumu_power_rating = cumu_power_rating + res.actual_power_rating
+      cumu_voltage_rating = cumu_voltage_rating + res.actual_voltage_rating
+      last_port = res.b
+    self.connect(last_port, self.b)
+    self.assign(self.actual_resistance, cumu_resistance)
+    self.assign(self.actual_power_rating, cumu_power_rating)
+    self.assign(self.actual_voltage_rating, cumu_voltage_rating)
+
+
 class PullupResistor(DiscreteApplication):
   """Pull-up resistor with an VoltageSink for automatic implicit connect to a Power line."""
   def __init__(self, resistance: RangeLike) -> None:
@@ -205,8 +252,12 @@ def generate(self):
       self.connect(self.io.append_elt(DigitalSource.empty(), requested), res.io)
 
 
-class SeriesPowerResistor(DiscreteApplication):
+class SeriesPowerResistor(DiscreteApplication, KiCadImportableBlock):
   """Series resistor for power applications"""
+  def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
+    assert symbol_name in ('Device:R', 'Device:R_Small')
+    return {'1': self.pwr_in, '2': self.pwr_out}
+
   def __init__(self, resistance: RangeLike) -> None:
     super().__init__()
 
@@ -324,3 +375,44 @@ def contents(self):
   def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]:
     assert symbol_name == 'Device:R'
     return {'1': self.signal_in, '2': self.signal_out}
+
+
+class DigitalClampResistor(Protection, KiCadImportableBlock):
+  """Inline resistor that limits the current (to a parameterized amount) which works in concert
+  with ESD diodes in the downstream device to clamp the signal voltage to allowable levels.
+
+  The protection voltage can be extended beyond the modeled range from the input signal,
+  and can also be specified to allow zero output voltage (for when the downstream device
+  is powered down)
+
+  TODO: clamp_target should be inferred from the target voltage_limits,
+  but voltage_limits doesn't always get propagated."""
+  def __init__(self, clamp_target: RangeLike = (0, 3)*Volt, clamp_current: RangeLike = (1.0, 10)*mAmp,
+               protection_voltage: RangeLike = (0, 0)*Volt, zero_out: BoolLike = False):
+    super().__init__()
+
+    self.signal_in = self.Port(DigitalSink.empty(), [Input])
+    self.signal_out = self.Port(DigitalSource.empty(), [Output])
+
+    self.clamp_target = self.ArgParameter(clamp_target)
+    self.clamp_current = self.ArgParameter(clamp_current)
+    self.protection_voltage = self.ArgParameter(protection_voltage)
+    self.zero_out = self.ArgParameter(zero_out)
+
+  def contents(self):
+    super().contents()
+
+    # TODO bidirectional clamping calcs?
+    self.res = self.Block(Resistor(resistance=1/self.clamp_current * self.zero_out.then_else(
+      self.signal_in.link().voltage.hull(self.protection_voltage).upper(),
+      self.signal_in.link().voltage.hull(self.protection_voltage).upper() - self.clamp_target.upper(),
+      )))
+    self.connect(self.res.a.adapt_to(DigitalSink(current_draw=self.signal_out.link().current_drawn)), self.signal_in)
+    self.connect(self.res.b.adapt_to(DigitalSource(
+      voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target),
+      output_thresholds=self.signal_in.link().output_thresholds
+    )), self.signal_out)
+
+  def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]:
+    assert symbol_name == 'Device:R'
+    return {'1': self.signal_in, '2': self.signal_out}

edg/abstract_parts/AbstractTestPoint.py

@@ -116,15 +116,15 @@ def connected(self, io: Port[AnalogLink]) -> 'AnalogTestPoint':
     return self
 
 
-class AnalogRfTestPoint(BaseRfTestPoint, Block):
-  """Test point with a AnalogSink port and 50-ohm matching resistor."""
+class AnalogCoaxTestPoint(BaseRfTestPoint, Block):
+  """Test point with a AnalogSink port and using a coax connector with shielding connected to gnd.
+  No impedance matching, this is intended for lower frequency signals where the wavelength would be
+  much longer than the test lead length"""
   def __init__(self, *args):
     super().__init__(*args)
-    self.res = self.Block(Resistor(50*Ohm(tol=0.05)))
-    self.io = self.Export(self.res.a.adapt_to(AnalogSink()), [InOut])
-    self.connect(self.res.b, self.conn.sig)
+    self.io = self.Export(self.conn.sig.adapt_to(AnalogSink()), [InOut])
 
-  def connected(self, io: Port[AnalogLink]) -> 'AnalogRfTestPoint':
+  def connected(self, io: Port[AnalogLink]) -> 'AnalogCoaxTestPoint':
     cast(Block, builder.get_enclosing_block()).connect(io, self.io)
     return self
 

edg/abstract_parts/DigitalAmplifiers.py

@@ -14,16 +14,16 @@ class HighSideSwitch(PowerSwitch, KiCadSchematicBlock, GeneratorBlock):
 
   TODO: clamp_voltage should be compared against the actual voltage so the clamp is automatically generated,
   but generators don't support link terms (yet?)"""
-  def __init__(self, pull_resistance: RangeLike = 10000*Ohm(tol=0.05), max_rds: FloatLike = 1*Ohm,
+  def __init__(self, pull_resistance: RangeLike = 10*kOhm(tol=0.05), max_rds: FloatLike = 1*Ohm,
                frequency: RangeLike = RangeExpr.ZERO, *,
                clamp_voltage: RangeLike = RangeExpr.ZERO, clamp_resistance_ratio: FloatLike = 10) -> None:
     super().__init__()
 
     self.pwr = self.Port(VoltageSink.empty(), [Power])  # amplifier voltage
     self.gnd = self.Port(Ground.empty(), [Common])
 
-    self.control = self.Port(DigitalSink.empty(), [Input])
-    self.output = self.Port(VoltageSource.empty(), [Output])
+    self.control = self.Port(DigitalSink.empty())
+    self.output = self.Port(VoltageSource.empty())
 
     self.pull_resistance = self.ArgParameter(pull_resistance)
     self.max_rds = self.ArgParameter(max_rds)

edg/abstract_parts/OpampCircuits.py

@@ -378,3 +378,26 @@ def contents(self) -> None:
       })
 
     self.assign(self.actual_factor, 1 / self.r.actual_resistance / self.c.actual_capacitance)
+
+
+class SummingAmplifier(OpampApplication):
+  @classmethod
+  def calculate_ratio(cls, resistances: List[Range]) -> List[Range]:
+    """Calculates each input's contribution to the output, for 1x gain.
+    Non-inverting summing amplifier topology.
+    Based on https://www.electronicshub.org/summing-amplifier/, which calculates the voltage of each input
+    and uses superposition to combine them."""
+    output = []
+    for i, resistance in enumerate(resistances):
+      # compute the two tolerance corners
+      others = resistances[:i] + resistances[i+1:]
+      other_lowest_parallel = 1 / sum([1 / other.lower for other in others])
+      other_highest_parallel = 1 / sum([1 / other.upper for other in others])
+      # ratio is lowest when this resistance is highest and other is lowest
+      ratio_lowest = other_lowest_parallel / (resistance.upper + other_lowest_parallel)
+      # ratio is highest when this resistance is lowest and other is highest
+      ratio_highest = other_highest_parallel / (resistance.lower + other_highest_parallel)
+
+      output.append(Range(ratio_lowest, ratio_highest))
+
+    return output