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Suke0811Suke0811
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Stm32g431 (#401)
This is the same as #400, but it removed the accidental commit/push of EspLora. Also applies the fix to the comments. - [x] #400 (comment) - [x] #400 (comment) - [x] #400 (comment) - [x] #400 (comment)
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‎edg/abstract_parts/IoControllerInterfaceMixins.py‎

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@@ -55,6 +55,14 @@ class IoControllerUsb(BlockInterfaceMixin[BaseIoController]):
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This WILL NOT WORK when used in .with_mixin, since this defines no fields."""
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pass
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class IoControllerUsbCc(BlockInterfaceMixin[BaseIoController]):
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def __init__(self, *args, **kwargs) -> None:
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super().__init__(*args, **kwargs)
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self.cc = self.Port(Vector(UsbCcPort.empty()), optional=True,
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doc="Microcontroller USB Power delivery CC pins")
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self.implementation(lambda base: base._io_ports.append(self.cc))
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class IoControllerI2s(BlockInterfaceMixin[BaseIoController]):
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def __init__(self, *args, **kwargs) -> None:

‎edg/abstract_parts/__init__.py‎

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from .IoController import BaseIoController, IoController, IoControllerPowerRequired, BaseIoControllerPinmapGenerator
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from .IoControllerExportable import BaseIoControllerExportable
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from .IoControllerInterfaceMixins import IoControllerSpiPeripheral, IoControllerI2cTarget, IoControllerTouchDriver,\
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IoControllerDac, IoControllerCan, IoControllerUsb, IoControllerI2s, IoControllerDvp8
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IoControllerDac, IoControllerCan, IoControllerUsb, IoControllerI2s, IoControllerDvp8, IoControllerUsbCc
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from .IoControllerInterfaceMixins import IoControllerPowerOut, IoControllerUsbOut, IoControllerVin
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from .IoControllerInterfaceMixins import IoControllerWifi, IoControllerBluetooth, IoControllerBle
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from .IoControllerProgramming import IoControllerWithSwdTargetConnector

‎edg/parts/Microcontroller_Stm32g431.py‎

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from typing import *
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from .JlcPart import JlcPart
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from ..abstract_parts import *
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@abstract_block
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class Stm32g431Base_Device(IoControllerI2cTarget, IoControllerCan, IoControllerUsb, InternalSubcircuit, IoControllerUsbCc,
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BaseIoControllerPinmapGenerator,
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GeneratorBlock, JlcPart, FootprintBlock):
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PACKAGE: str # package name for footprint(...)
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PART: str # part name for footprint(...)
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LCSC_PART: str
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LCSC_BASIC_PART: bool
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SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s)
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RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
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def __init__(self, **kwargs) -> None:
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super().__init__(**kwargs)
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# Power and ground
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self.pwr = self.Port(VoltageSink(
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voltage_limits=(1.71, 3.6) * Volt,
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current_draw=(14 * nAmp, 44.0 * mAmp) # Table 32
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), [Power])
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self.gnd = self.Port(Ground(), [Common])
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self.swd = self.Port(SwdTargetPort.empty())
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self._io_ports.insert(0, self.swd)
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self.nrst = self.Port(DigitalSink.empty(), optional=True) # internally pulled up
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def _system_pinmap(self) -> Dict[str, CircuitPort]:
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return VariantPinRemapper({
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'Vdd': self.pwr,
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'Vss': self.gnd,
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# 'VddA': self.pwr,
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# 'VssA': self.gnd,
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'BOOT0': self.gnd,
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'PG10-NRST': self.nrst,
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}).remap(self.SYSTEM_PIN_REMAP)
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def _io_pinmap(self) -> PinMapUtil:
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input_range = self.gnd.link().voltage.hull(self.pwr.link().voltage)
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io_voltage_limit = (input_range + (-0.3, 3.6) * Volt).intersect(
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self.gnd.link().voltage + (-0.3, 5.5) * Volt) # Section 5.3.1
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input_threshold_factor = (0.3, 0.7) # Section 5.3.14
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current_limits = (-20, 20) * mAmp # Table 15
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dio_ft_model = DigitalBidir.from_supply(
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self.gnd, self.pwr,
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voltage_limit_abs=io_voltage_limit,
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current_limits=current_limits,
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input_threshold_factor=input_threshold_factor,
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pullup_capable=True, pulldown_capable=True
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)
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dio_tt_model = DigitalBidir.from_supply(
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self.gnd, self.pwr,
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voltage_limit_tolerance=(-0.3, 0.3) * Volt, # Table 19
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current_draw=(0, 0) * Amp, current_limits=current_limits,
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input_threshold_factor=input_threshold_factor,
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pullup_capable=True, pulldown_capable=True
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)
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# Pin definition, 4.10
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dio_fta_model = dio_ftca_model = dio_ftf_model = dio_ftfa_model = \
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dio_ftfu_model = dio_ftfd_model = dio_ftda_model = dio_ftu_model = dio_ft_model
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dio_tta_model = dio_tt_model
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dio_ftc_model = DigitalBidir.from_supply(
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self.gnd, self.pwr,
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voltage_limit_abs=(-0.3, 5.0) * Volt,
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current_limits=current_limits,
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input_threshold_factor=input_threshold_factor,
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pullup_capable=True, pulldown_capable=True
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)
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adc_model = AnalogSink.from_supply(
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self.gnd, self.pwr,
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voltage_limit_tolerance=(-0.3, 0.3) * Volt,
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signal_limit_tolerance=(0, 0),
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impedance=(50, float('inf')) * kOhm # TODO: this is maximum external input impedance, maybe restrictive
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)
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dac_model = AnalogSource.from_supply(
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self.gnd, self.pwr,
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signal_out_bound=(0.2 * Volt, -0.2 * Volt), # signal_out_bound only applies when output buffer on
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impedance=(9.6, 13.8) * kOhm # assumes buffer off
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)
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self.nrst.init_from(DigitalSink.from_supply( # specified differently than other pins
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self.gnd, self.pwr,
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voltage_limit_abs=io_voltage_limit, # assumed
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input_threshold_factor=(0.3, 0.7),
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pullup_capable=True # internal pullup
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))
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uart_model = UartPort(DigitalBidir.empty())
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spi_model = SpiController(DigitalBidir.empty())
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i2c_model = I2cController(DigitalBidir.empty())
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i2c_target_model = I2cTarget(DigitalBidir.empty())
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return PinMapUtil([ # for 32 pins only for now
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PinResource('PF0', {'PF0': dio_ftfa_model, 'ADC1_IN10': adc_model}), # TODO remappable to OSC_IN
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PinResource('PF1', {'PF1': dio_fta_model, 'ADC2_IN10': adc_model}), # TODO remappable to OSC_OUT
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PinResource('PA0', {'PA0': dio_tta_model, 'ADC12_IN1': adc_model}),
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PinResource('PA1', {'PA1': dio_tta_model, 'ADC12_IN2': adc_model}),
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PinResource('PA2', {'PA2': dio_tta_model, 'ADC1_IN3': adc_model}),
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PinResource('PA3', {'PA3': dio_tta_model, 'ADC1_IN4': adc_model}),
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PinResource('PA4', {'PA4': dio_tta_model, 'ADC2_IN17': adc_model, 'DAC1_OUT1': dac_model}),
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PinResource('PA5', {'PA5': dio_tta_model, 'ADC2_IN13': adc_model, 'DAC1_OUT2': dac_model}),
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PinResource('PA6', {'PA6': dio_tta_model, 'ADC2_IN3': adc_model}),
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PinResource('PA7', {'PA7': dio_tta_model, 'ADC2_IN4': adc_model}),
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PinResource('PA8', {'PA8': dio_ftf_model}),
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PinResource('PA9', {'PA9': dio_ftfd_model}),
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PinResource('PA10', {'PA10': dio_ftda_model}),
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PinResource('PA11', {'PA11': dio_ftu_model}), # USB_DM
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PinResource('PA12', {'PA12': dio_ftu_model}), # USB_DP
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PinResource('PA13', {'PA13': dio_ftf_model}),
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PinResource('PA14', {'PA14': dio_ftf_model}),
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PinResource('PA15', {'PA15': dio_ftf_model}),
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PinResource('PB0', {'PB0': dio_tta_model, 'ADC1_IN15': adc_model}),
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PinResource('PB3', {'PB3': dio_ft_model}),
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PinResource('PB4', {'PB4': dio_ftc_model}),
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PinResource('PB5', {'PB5': dio_ftf_model}),
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PinResource('PB6', {'PB6': dio_ftc_model}),
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PinResource('PB7', {'PB7': dio_ftf_model}),
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PinResource('PB8', {'PB8': dio_ftf_model}),
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# From table 13
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PeripheralFixedResource('SPI1', spi_model, {
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'sck': ['PA5', 'PB3'], 'miso': ['PA6', 'PB4'], 'mosi': ['PA7', 'PB5']
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}),
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PeripheralFixedResource('SPI2', spi_model, {
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'sck': ['PF1'], 'miso': ['PA10'], 'mosi': ['PA11']
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}),
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PeripheralFixedResource('SPI3', spi_model, {
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'sck': ['PB3'], 'miso': ['PB4'], 'mosi': ['PB5']
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}),
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PeripheralFixedResource('I2S2', I2sController(DigitalBidir.empty()), {
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'sck': ['PB13', 'PF1'], 'ws': ['PB12', 'PF0'], 'sd': ['PA11', 'PB15']
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}),
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PeripheralFixedResource('I2S3', I2sController(DigitalBidir.empty()), {
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'sck': ['PB3'], 'ws': ['PA4', 'PA15'], 'sd': ['PB5']
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}),
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PeripheralFixedResource('USART1', uart_model, {
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'tx': ['PA9', 'PB6'], 'rx': ['PA10', 'PB7']
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}),
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PeripheralFixedResource('USART2', uart_model, {
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'tx': ['PA2', 'PA14', 'PB3'], 'rx': ['PA3', 'PA15', 'PB4']
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}),
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PeripheralFixedResource('USART3', uart_model, {
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'tx': ['PB9', 'PB10'], 'rx': ['PB8', 'PB11', ]
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}),
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PeripheralFixedResource('LPUART1', uart_model, {
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'tx': ['PA2', 'PB11'], 'rx': ['PA3', 'PB10']
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}),
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PeripheralFixedResource('I2C1', i2c_model, {
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'scl': ['PA13', 'PA15', 'PB8'], 'sda': ['PA14', 'PB7', 'PB9']
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}),
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PeripheralFixedResource('I2C1_T', i2c_target_model, {
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'scl': ['PA13', 'PA15', 'PB8'], 'sda': ['PA14', 'PB7', 'PB9']
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}),
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PeripheralFixedResource('I2C2', i2c_model, {
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'scl': ['PA9'], 'sda': ['PA8', 'PF0']
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}),
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PeripheralFixedResource('I2C2_T', i2c_target_model, {
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'scl': ['PA9'], 'sda': ['PA8', 'PF0']
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}),
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PeripheralFixedResource('I2C3', i2c_model, {
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'scl': ['PA8'], 'sda': ['PB5']
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}),
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PeripheralFixedResource('FDCAN', CanControllerPort(DigitalBidir.empty()), {
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'tx': ['PA12', 'PB9'], 'rx': ['PA11', 'PB8']
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}),
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PeripheralFixedResource('SWD', SwdTargetPort(DigitalBidir.empty()), {
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'swdio': ['PA13'], 'swclk': ['PA14'],
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}),
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PeripheralFixedResource('USB', UsbDevicePort(DigitalBidir.empty()), {
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'dm': ['PA11'], 'dp': ['PA12']
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}),
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PeripheralFixedResource('USBCC', UsbCcPort(pullup_capable=True), {
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'cc1': ['PB6'], 'cc2': ['PB4']
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}),
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]).remap_pins(self.RESOURCE_PIN_REMAP)
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def generate(self) -> None:
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super().generate()
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self.footprint(
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'U', self.PACKAGE,
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self._make_pinning(),
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mfr='STMicroelectronics', part=self.PART,
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datasheet='https://www.st.com/resource/en/datasheet/stm32g431kb.pdf'
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)
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self.assign(self.lcsc_part, self.LCSC_PART)
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self.assign(self.actual_basic_part, False)
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class Stm32g431_G_Device(Stm32g431Base_Device):
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SYSTEM_PIN_REMAP = {
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'Vdd': ['1', '15', '17'], # 15 VDDA
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'Vss': ['14', '16', '32'], # 14 VSSA
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'BOOT0': '31',
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'PG10-NRST': '4',
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}
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RESOURCE_PIN_REMAP = {
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'PF0': '2',
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'PF1': '3',
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'PA0': '5',
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'PA1': '6',
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'PA2': '7',
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'PA3': '8',
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'PA4': '9',
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'PA5': '10',
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'PA6': '11',
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'PA7': '12',
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'PA8': '18',
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'PA9': '19',
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'PA10': '20',
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'PA11': '21',
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'PA12': '22',
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'PA13': '23',
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'PA14': '24',
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'PA15': '25',
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'PB0': '13',
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'PB3': '26',
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'PB4': '27',
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'PB5': '28',
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'PB6': '29',
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'PB7': '30',
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}
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PACKAGE = 'Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm'
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PART = 'STM32G431KB'
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LCSC_PART = 'C1341901' # STM32G431KBU3
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@abstract_block
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class Stm32g431Base(Resettable, IoControllerI2cTarget, Microcontroller, IoControllerWithSwdTargetConnector,
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IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock):
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DEVICE: Type[Stm32g431Base_Device] = Stm32g431Base_Device
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def __init__(self, **kwargs):
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super().__init__(**kwargs)
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self.ic: Stm32g431Base_Device
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self.generator_param(self.reset.is_connected())
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def contents(self):
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super().contents()
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with self.implicit_connect(
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ImplicitConnect(self.pwr, [Power]),
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ImplicitConnect(self.gnd, [Common])
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) as imp:
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self.ic = imp.Block(self.DEVICE(pin_assigns=ArrayStringExpr()))
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self.connect(self.swd_node, self.ic.swd)
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self.connect(self.reset_node, self.ic.nrst)
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# from https://www.st.com/resource/en/application_note/an5093-getting-started-with-stm32g4-series--hardware-development-boards-stmicroelectronics.pdf
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self.pwr_cap0 = imp.Block(DecouplingCapacitor(10 * uFarad(tol=0.2)))
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# from the above pdf, we need 100nF per number of VDD
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self.pwr_cap1 = imp.Block(DecouplingCapacitor(100 * nFarad(tol=0.2)))
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self.pwr_cap2 = imp.Block(DecouplingCapacitor(100 * nFarad(tol=0.2)))
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self.pwr_cap3 = imp.Block(DecouplingCapacitor(100 * nFarad(tol=0.2)))
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self.pwr_cap4 = imp.Block(DecouplingCapacitor(1 * uFarad(tol=0.2)))
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def generate(self):
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super().generate()
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if self.get(self.reset.is_connected()):
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self.connect(self.reset, self.ic.nrst) # otherwise NRST has internal pull-up
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class Stm32g431kb(Stm32g431Base):
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DEVICE = Stm32g431_G_Device

‎edg/parts/__init__.py‎

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from .Microcontroller_Stm32f103 import Stm32f103_48
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from .Microcontroller_Stm32f303 import Nucleo_F303k8
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from .Microcontroller_Stm32g031 import Stm32g031_G
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from .Microcontroller_Stm32g431 import Stm32g431kb
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from .Microcontroller_Stm32l432 import Stm32l432k
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from .Microcontroller_nRF52840 import Holyiot_18010, Mdbt50q_1mv2, Feather_Nrf52840
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from .Microcontroller_Esp import EspProgrammingHeader, EspProgrammingAutoReset, EspProgrammingPinHeader254, EspProgrammingTc2030

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