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Initial support for Obsidian in badger/tests
rgmii_hw_test works on hardware Very slight rework of conditional code in rgmii_hw_test.v
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‎badger/tests/Makefile‎

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@@ -270,6 +270,14 @@ marblem_rgmii_vtest.bit: marblem_rgmii_test.tcl marblem_rgmii_test.d badger.tcl
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$(SYNTH_VIVADO) $<
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mv _xilinx/marblem_rgmii_test.runs/impl_1/rgmii_hw_test.bit $@
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# =====
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SYNTH_SOURCE_OBSIDIAN = rgmii_hw_test.v gmii_to_rgmii.v $(HW_TEST_V) marble/gmii_clock_handle.v $(FPGA_FAMILY_DIR)/xilinx/xilinx7_clocks.v
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obsidian_rgmii_test.d: $(SYNTH_SOURCE_OBSIDIAN) obsidian/obsidian_rgmii.xdc
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echo $^ | tr ' ' '\n' > $@
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obsidian_rgmii_vtest.bit: obsidian_rgmii_test.tcl obsidian_rgmii_test.d badger.tcl $(SYNTH_SOURCE_OBSIDIAN) obsidian/obsidian_rgmii.xdc
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$(SYNTH_VIVADO) $<
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mv _xilinx/obsidian_rgmii_test.runs/impl_1/rgmii_hw_test.bit $@
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# =====
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# On-line test using Icarus and Linux's tun/tap feature
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rtefi_live: rtefi_pipe_tb.v $(RTEFI_V) fake_config_romx.v mac_compat_dpram.v tap-vpi.vpi

‎badger/tests/marblem_rgmii_test.tcl‎

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@@ -2,5 +2,5 @@ source "badger.tcl"
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set build_id "marblem_rgmii_test"
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set chip_id "xc7a100t-fgg484-2"
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set top_module "rgmii_hw_test"
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set verilog_defines [list "CHIP_FAMILY_7SERIES" "MARBLE_TEST"]
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set verilog_defines [list "CHIP_FAMILY_7SERIES" "MARBLE_TEST" "USE_IN_PHASE_PHY_CLK"]
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badger_build $build_id $chip_id $top_module $verilog_defines

‎badger/tests/obsidian/obsidian_rgmii.xdc‎

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# Obsidian
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# https://github.com/BerkeleyLab/Obsidian
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# compare and contrast the contents of this file with
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# https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/berkeleylab_obsidian.py
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# RGMII PHY
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports PHY_RSTN]
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports RGMII_RX_CLK]
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports RGMII_RX_CTRL]
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {RGMII_RXD[0]}]
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {RGMII_RXD[1]}]
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {RGMII_RXD[2]}]
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33} [get_ports {RGMII_RXD[3]}]
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports RGMII_TX_CLK]
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports RGMII_TX_CTRL]
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {RGMII_TXD[0]}]
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {RGMII_TXD[1]}]
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set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {RGMII_TXD[2]}]
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set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {RGMII_TXD[3]}]
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# https://adaptivesupport.amd.com/s/article/53092?language=en_US
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set_property IOB TRUE [get_ports {RGMII_TXD[*]}]
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set_property IOB TRUE [get_ports RGMII_TX_CTRL]
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set_property IOB TRUE [get_ports {RGMII_RXD[*]}]
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set_property IOB TRUE [get_ports RGMII_RX_CTRL]
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# Rx clock constraint
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create_clock -period 8.00 -name phy_rxclk [get_ports RGMII_RX_CLK]
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# QSPI Boot Flash
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports BOOT_CS_B]
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set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports BOOT_MOSI]
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports BOOT_MISO]
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# FPGA_CCLK is special, and doesn't show up here;
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# access is accomplished by instantiating the STARTUPE2 primitive
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# LEDs
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set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {LED[0]}]
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set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {LED[1]}]
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set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {LED[2]}]
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set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {LED[3]}]
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# LED_0 connects to PMOD1_0
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# LED_1 connects to PMOD1_1
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# LED_2 connects to PMOD1_2
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# LED_3 connects to PMOD1_3
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# To gain access to these blinkenlights, it's suggested to plug in a
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# usual Diglent PmodLED to the top half of J4 (a.k.a. PMOD1).
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# Possible connection to supervisory microcontroller
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# Want actual pins here so the synthesizer doesn't drop the supporting logic;
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# I have no short-term plans to exercise these pins in hardware.
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# See projects/test_marble_family to demo that feature.
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# SCLK connects to PMOD1_4
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# CSB connects to PMOD1_5
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# MOSI connects to PMOD1_6
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set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports SCLK]
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports CSB]
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports MOSI]
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# 125 MHz from White Rabbit comes in via MGTREFCLK;
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# we should really turn on the GTP and use its TXOUTCLK.
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# 20 MHz CLK20_VCXO from Y3 is a poor substitute
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set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports SYSCLK_P]
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create_clock -name sys_clk -period 50.00 [get_ports SYSCLK_P]
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# this property setting is correct: the CLK20_VCXO pin is only used for its _frequency_, not as a phase
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SYSCLK_P]
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# Miscellaneous
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# Accidentally unavailable; substitute PMOD1_7, and trust that the
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# unconnected Y3-2 will float high (R176 should help)
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports VCXO_EN]
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# RESET not actually used in gateware or available on hardware
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# Assign it to PMOD2_0 anyway
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set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports RESET]
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# Clock groups
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set_clock_groups -name async_clks -asynchronous \
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-group [get_clocks -include_generated_clocks sys_clk] \
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-group [get_clocks -include_generated_clocks phy_rxclk]
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# Bank 0 setup
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]

‎badger/tests/obsidian_rgmii_test.tcl‎

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source "badger.tcl"
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set build_id "obsidian_rgmii_test"
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set chip_id "xc7a35t-csg325-2"
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set top_module "rgmii_hw_test"
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set verilog_defines [list "CHIP_FAMILY_7SERIES" "MARBLE_TEST"]
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badger_build $build_id $chip_id $top_module $verilog_defines

‎badger/tests/rgmii_hw_test.v‎

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// RGMII Hardware Test
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// mostly just instantiates hw_test
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// Initial target is AC701
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// Initial target is AC701; also used for Marble-Mini and Obsidian
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module rgmii_hw_test(
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// 200 MHz typical
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// 200 MHz differential on AC701
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input SYSCLK_P,
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`ifndef MARBLE_TEST
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input SYSCLK_N,
@@ -46,12 +46,14 @@ module rgmii_hw_test(
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`ifdef MARBLE_TEST
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assign VCXO_EN = 1;
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wire SYSCLK_N = 0;
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`endif
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`ifdef USE_IN_PHASE_PHY_CLK
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parameter in_phase_tx_clk = 1;
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`else
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parameter in_phase_tx_clk = 0;
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`endif
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// Standardized interface, hardware-dependent implementation
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// Standardized interface, with hardware-dependent implementation
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wire tx_clk, tx_clk90;
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wire clk_locked;
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wire pll_reset = 0; // or RESET?

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