Merge branch 'numpy_compt' into 'master'

Numpy version > 2.X compatibility

See merge request hdl-libraries/bedrock!249

Author: dchabot

Dockerfile.bedrock_testing_base_bookworm

@@ -135,7 +135,7 @@ RUN mkdir ${LITEX_INSTALL_PATH} && \
 
 # Install leep from PyPi
 RUN pip3 install \
-    leep==1.0.1
+    leep==1.0.2
 
 # Install sv2v
 RUN apt-get update && \

Dockerfile.bedrock_testing_base_trixie

@@ -135,7 +135,7 @@ RUN mkdir ${LITEX_INSTALL_PATH} && \
 
 # Install leep from PyPi
 RUN pip3 install \
-    leep==1.0.1
+    leep==1.0.2
 
 # Install sv2v
 RUN apt-get update && \

board_support/zest/ad7794.py

@@ -90,6 +90,7 @@ def configuration_register(self, chan):
         return val | 0x0000ff
 
     def conv_volt(self, readout, chan):
+        readout = int(readout)
         vref = 0.0
         if chan == 6 or self.REFSEL == 2:
             vref = 1.17

board_support/zest/zest_setup.py

@@ -158,7 +158,8 @@ def hardware_reset(self, injector=False):
             if not self.pntest4():
                 return False
         self.adc_twos_comp(twoscomp=True)
-        print('test pattern %s' % self.set_test_mode('00000000'))
+        print('test pattern %s' % "".join([
+              str(item) for sublist in self.set_test_mode('00001100') or [] for item in sublist]))
         if not self.amc7823_print(check_channels=[1, 2, 3, 4, 5, 6, 7]):
             return False
         return True
@@ -575,7 +576,8 @@ def find_best_idelay(self, ix, idelay_dict):
         return ix if False else self.top2idelay(lane, ix % 2)[0]
 
     def adc_idelay1(self, dbg1=0):
-        print('test pattern %s' % self.set_test_mode('00001100'))
+        print('test pattern %s' % "".join([
+              str(item) for sublist in self.set_test_mode('00001100') or [] for item in sublist]))
         print('Type 1 (firmware) idelay scan')
         if True:  # not needed after powerup, but will clear old values if re-scanning
             self.set_idelays(16*[0])
@@ -605,7 +607,8 @@ def adc_idelay1(self, dbg1=0):
         return all([2 == (x >> 5) for x in idelay_mirror])  # all channels scan success!
 
     def adc_idelay0(self):
-        print('test pattern %s' % self.set_test_mode('00001100'))
+        print('test pattern %s' % "".join([
+              str(item) for sublist in self.set_test_mode('00001100') or [] for item in sublist]))
         print('Type 0 (software) idelay scan')
         print("idelay  scan   " + "  ".join(self.chan_list))
         idelay_dict = {}
@@ -651,7 +654,8 @@ def adc_bufr_reset1(self, adc_values, name, adc, ic_reset, iserdes_reset):
         return success, adc_values
 
     def adc_bufr_reset(self):
-        print('test pattern %s' % self.set_test_mode('00001100'))
+        print('test pattern %s' % "".join([
+              str(item) for sublist in self.set_test_mode('00001100') or [] for item in sublist]))
         adc_values = self.adc_reg(verbose=True)
         print('0x%x %s %s' % (adc_values[0], adc_values[0] != 0x4339, adc_values[0] != 0xa19c))
         s1, adc_values = self.adc_bufr_reset1(
@@ -661,7 +665,8 @@ def adc_bufr_reset(self):
         return s1 and s2
 
     def adc_bitslip(self):
-        print('bitslip: test pattern %s' % self.set_test_mode('00001100'))
+        print('bitslip test pattern %s' % "".join([
+              str(item) for sublist in self.set_test_mode('00001100') or [] for item in sublist]))
         index = 0
         bitslip = self.bitslip_calc()
         print(format(bitslip, '016b'))

projects/common/get_raw_adcs.py

@@ -68,7 +68,8 @@ def get_raw_adcs_run(dev, filewritepath='raw_adcs_', ext_trig=False, freq=7/33.0
             print("difference %6.2f" % diff1)
         if save_data is True:
             # ISO 8601  2016-06-02T16:06:14Z
-            datetimestr = datetime.datetime.utcnow().isoformat()+"Z "+str(timestamp)
+            dt_now = datetime.datetime.now(datetime.timezone.utc)
+            datetimestr = dt_now.isoformat().replace('+00:00', 'Z') + " " + str(timestamp)
             header = "\n".join([datetimestr, chan_txt])
 
             data_dir = start_time.strftime(filewritepath + '%Y%m%d_%H%M%S')
@@ -216,7 +217,7 @@ def process_adcs(dev, npt, mask_int, freq=7/33.0):  # ,block,timestamp):
 
 
 def slow_chain_unpack(readlist):
-    nums = [256*readlist[ix]+readlist[ix+1] for ix in range(0, 32, 2)]
+    nums = [int(readlist[ix])*256 + int(readlist[ix+1]) for ix in range(0, 32, 2)]
     nums = [x if x < 32768 else x-65536 for x in nums]
     timestamp = 0
     for ix in range(8):

projects/test_marble_family/config_si570.py

@@ -5,7 +5,6 @@
 # tested on marble_mmc branch marble_v1_4 commit 80a96fc6
 # but also backward compatible because of default values
 import sys
-import numpy as np
 bedrock_dir = "../../"
 sys.path.append(bedrock_dir + "peripheral_drivers/i2cbridge")
 sys.path.append(bedrock_dir + "badger")
@@ -185,9 +184,10 @@ def compute_si570(addr, key, verbose=False, debug=False):
     ib = 3*32  # init result memory base, derived from set_resx(3)
     a = result[ib+1:ib+7]
 
-    hs_div = (a[0] >> 5) + 4
-    n1 = (((a[0] & 0x1f) << 2) | (a[1] >> 6)) + 1
-    rfreq = np.uint64((((a[1] & 0x3f) << 32) | (a[2] << 24) | (a[3] << 16) | (a[4] << 8) | a[5])) / (2**28)
+    hs_div = int(a[0] >> 5) + 4
+    n1 = int(((a[0] & 0x1f) << 2) | (a[1] >> 6)) + 1
+    rfreq_int = (int(a[1]) & 0x3f) << 32 | int(a[2]) << 24 | int(a[3]) << 16 | int(a[4]) << 8 | int(a[5])
+    rfreq = float(rfreq_int) / float(2**28)
 
     freq_default = addr.reg_read(["frequency_si570"])
     default = (freq_default[0]/2**24.0)*125

projects/test_marble_family/testcase.py

@@ -1,6 +1,5 @@
 from time import sleep
 import sys
-import numpy as np
 bedrock_dir = "../../"
 sys.path.append(bedrock_dir + "peripheral_drivers/i2cbridge")
 sys.path.append(bedrock_dir + "badger")
@@ -12,7 +11,7 @@
 # return an n-long array of 16-bit values, still integer
 # constructed assuming 8-bit values are arranged in pairs, msb-first
 def merge_16(a):
-    aa = [x1*256+x2 for x1, x2 in zip(a[0::2], a[1::2])]
+    aa = [int(x1)*256 + int(x2) for x1, x2 in zip(a[0::2], a[1::2])]
     return aa
 
 
@@ -180,9 +179,9 @@ def compute_si570(freq_default, a):
     # DCO frequency range: 4850 - 5670MHz
     # HSDIV values: 4, 5, 6, 7, 9 or 11 (subtract 4 to store)
     # N1 values: 1, 2, 4, 6, 8...128
-    hs_div = (a[0] >> 5) + 4
-    n1 = (((a[0] & 0x1f) << 2) | (a[1] >> 6)) + 1
-    rfreq = np.uint64((((a[1] & 0x3f) << 32) | (a[2] << 24) | (a[3] << 16) | (a[4] << 8) | a[5])) / (2**28)
+    hs_div = int(a[0] >> 5) + 4
+    n1 = int(((a[0] & 0x1f) << 2) | (a[1] >> 6)) + 1
+    rfreq = float(int((a[1] & 0x3f) << 32 | a[2] << 24 | a[3] << 16 | a[4] << 8 | a[5])) / float(2**28)
 
     default = (freq_default[0]/2**24.0)*125
     fxtal = default * hs_div * n1 / rfreq