Merge branch 'cmoc_updates' into 'master'

cmoc on marble

* Enables cmoc on Marble board and adds CI rule to synthesize a bitfile.
* To differentiate between the boards, add projects/cmoc_top/marblemini/marble_features.yaml.
* Add new projects/test_marble_family/marble_mid.vh middle layer that can be reused between cmoc_top.v and marble_top.v.

See merge request hdl-libraries/bedrock!220

Author: ldoolitt

.gitlab/ci/cmoc.gitlab-ci.yml

@@ -12,12 +12,15 @@ cmoc_test:
   script:
     - make && make checks
 
-cmoc_top_marblemini:
+cmoc_top:
   before_script:
     - cd projects/cmoc_top/marblemini && ls /non-free
   stage: synthesis
   script:
-    - XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make HARDWARE=marblemini cmoc_top.bit
+    - XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make HARDWARE=${TARGET} cmoc_top.bit
+  parallel:
+    matrix:
+      - TARGET: [marblemini, marble]
   artifacts:
     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
     expire_in: 1 week

cmoc/cryomodule_badger.v

@@ -31,7 +31,7 @@ wire [23:0] rtefi_lb_addr;
 wire [31:0] rtefi_lb_data_out;
 wire [31:0] rtefi_lb_data_in;
 
-
+// TODO: Add option to let MMC set the IP address and MAC
 rtefi_blob #(.ip(ip), .mac(mac)) badger(
 	// GMII Input (Rx)
 	.rx_clk(gmii_rx_clk),

cmoc/cryomodule_test_setup.py

@@ -3,12 +3,8 @@
 from math import pi, sqrt, log
 from numpy import exp as cexp
 from numpy import ceil
-# https://stackoverflow.com/questions/14132789/relative-imports-for-the-billionth-time
-# Leaves me with only one choice ... :(
-# Since I don't want to modify shell variables
-sys.path.append(
-    os.path.dirname(os.path.dirname(os.path.abspath(__file__))) +
-    "/../build-tools")
+
+sys.path.append(os.path.join(os.path.dirname(__file__), "../build-tools"))
 from read_regmap import get_map, get_reg_info
 
 cav_num = 0

projects/cmoc_top/marblemini/Makefile

@@ -3,15 +3,15 @@ include $(TOP_DIR)/dir_list.mk
 .PHONY: all
 all: $(TARGET)
 
-HARDWARE = marblemini
-DSP_FLAVOR = 7
 XILINX_TOOL := VIVADO
-
 APP_NAME = cmoc
 
+HARDWARE = marblemini
+
 APP_DIR = $(TOP_DIR)/cmoc
 DSP_DIR = $(TOP_DIR)/dsp
 OSCOPE_COMMON_DIR = $(TOP_DIR)/projects/oscope/common
+TEST_MARBLE_FAMILY = $(TOP_DIR)/projects/test_marble_family
 BS_HARDWARE_DIR = $(BOARD_SUPPORT_DIR)/$(HARDWARE)
 
 vpath %.v $(APP_DIR) $(RTSIM_DIR) $(DSP_DIR) $(DSP_DIR)/hosted $(BADGER_DIR)
@@ -24,19 +24,20 @@ include $(APP_DIR)/rules.mk
 
 SYNTH_OPT += $(VERILOG_DEFINE_FLAGS)
 
-VFLAGS_DEP += -y$(BS_HARDWARE_DIR) -y$(BOARD_SUPPORT_DIR)/marblemini -y$(FPGA_FAMILY_DIR) -y$(FPGA_FAMILY_DIR) -y$(FPGA_FAMILY_DIR)/xilinx -y$(FPGA_FAMILY_DIR)/pll -y. -y$(APP_DIR) -y$(HOMELESS_DIR) -y$(HOMELESS_DIR)/freq_demo -y$(BADGER_DIR) -y$(BADGER_DIR)/tests -y$(BADGER_DIR)/tests/kc705 -y$(SERIAL_IO_DIR) -y../../test_marble_family -y../../test_marble_family/pps_lock -y$(PERIPH_DRIVERS_DIR) -y$(PERIPH_DRIVERS_DIR)/i2cbridge -y../bmb7_cu
+VFLAGS_DEP += -y$(BS_HARDWARE_DIR) -y$(BOARD_SUPPORT_DIR)/marblemini -y$(FPGA_FAMILY_DIR) -y$(FPGA_FAMILY_DIR) -y$(FPGA_FAMILY_DIR)/xilinx -y$(FPGA_FAMILY_DIR)/pll -y. -y$(APP_DIR) -y$(HOMELESS_DIR) -y$(HOMELESS_DIR)/freq_demo -y$(BADGER_DIR) -y$(BADGER_DIR)/tests -y$(BADGER_DIR)/tests/kc705 -y$(SERIAL_IO_DIR) -y$(TEST_MARBLE_FAMILY) -I$(TEST_MARBLE_FAMILY) -y$(TEST_MARBLE_FAMILY)/pps_lock -y$(PERIPH_DRIVERS_DIR) -y$(PERIPH_DRIVERS_DIR)/i2cbridge -y../bmb7_cu
 
 VFLAGS += $(VERILOG_DEFINE_FLAGS)
 
-system_top.xdc: $(BOARD_SUPPORT_DIR)/$(HARDWARE)/Marble.xdc $(BOARD_SUPPORT_DIR)/$(HARDWARE)/pin_map.csv digilent_led_pmod.csv oscope_rules.csv
+system_top.xdc: $(BOARD_SUPPORT_DIR)/$(HARDWARE)/Marble.xdc $(BOARD_SUPPORT_DIR)/$(HARDWARE)/pin_map.csv $(HARDWARE)_top.csv
 	@echo "Building for $(HARDWARE); Use make HARDWARE=marble(mini) otherwise"
 	$(PYTHON) $(BADGER_DIR)/tests/meta-xdc.py $^ > $@
 
-CLEAN += $(TARGET) $(AUTOGEN_DIR)/config_romx.v *~ system_top.xdc cmoc_top.bin cmoc_top.prm cmoc_top.bit $(APP_NAME)_regmap_long.json $(APP_NAME)_regmap.json $(RTEFI_CLEAN)
+CLEAN += $(TARGET) $(AUTOGEN_DIR)/config_romx.v *~ system_top.xdc cmoc_top.bin cmoc_top.prm cmoc_top.bit $(APP_NAME)_regmap_long.json $(APP_NAME)_regmap.json marble_features*.vh $(RTEFI_CLEAN)
+CLEAN += *.log *.jou
 CLEAN_DIRS += _xilinx
 
 cmoc_top.bit: $(AUTOGEN_DIR)/config_romx.v
-cmoc_top.v: $(AUTOGEN_DIR)/config_romx.v rtefi_blob.v construct_tx_table.v cryomodule_auto
+cmoc_top.v: marble_features_defs.vh marble_features_params.vh $(AUTOGEN_DIR)/config_romx.v rtefi_blob.v construct_tx_table.v cryomodule_auto
 
 download: cmoc_top.bit
 	openocd -f $(BOARD_SUPPORT_DIR)/$(HARDWARE)/marble.cfg -c "transport select jtag; init; xc7_program xc7.tap; pld load 0 $^; exit"
@@ -50,6 +51,10 @@ $(APP_NAME)_regmap.json: $(AUTOGEN_DIR)/regmap_cryomodule.json $(OSCOPE_COMMON_D
 	$(PYTHON) $(OSCOPE_COMMON_DIR)/merge_json.py -o $(APP_NAME)_regmap_long.json -i $(filter %.json, $^)
 	$(PYTHON) $(OSCOPE_COMMON_DIR)/shorten_names.py -o $@ -i $(APP_NAME)_regmap_long.json
 
+# actual file output is marble_features_(defs/params).vh
+marble_features_defs.vh marble_features_params.vh: $(BUILD_DIR)/gen_features.py $(TEST_MARBLE_FAMILY)/marble_features.yaml
+	$(PYTHON) $< -i $(filter %.yaml, $^) -c $(HARDWARE) --split
+
 include $(BUILD_DIR)/bottom_rules.mk
 
 ifneq (,$(findstring bit,$(MAKECMDGOALS)))