badger: refresh documentation related to Spartan-6 resources

Update status.md with more software versions
Make "make bits" work better

Author: ldoolitt

badger/construct.v

@@ -17,7 +17,7 @@ module construct #(
 	// allowance Rx/Tx frequency offset.
 	// At the other end, p_offset + max(fp_offset) < (2048-MTU-guard)
 ) (
-	input clk,
+	input clk,  // timespec 6.8 ns
 	input [paw-1:0] gray_state,
 	// port to MAC/IP config, single-cycle latency
 	output [3:0] ip_a,

badger/ethernet_crc_add.v

@@ -6,7 +6,7 @@
 // raw_s is valid just for the (incoming) packet data.
 // raw_l is also valid for a few cycles before, and 4 cycles after, that.
 module ethernet_crc_add(
-	input clk,
+	input clk,  // timespec 6.8 ns
 	input raw_s,
 	input raw_l,
 	input [7:0] raw_d,

badger/scanner.v

@@ -21,7 +21,7 @@
 // The four submodules have relatively consistent ports and semantics.
 
 module scanner (
-	input clk,
+	input clk,  // timespec 6.8 ns
 	input [7:0] eth_in,
 	input eth_in_s,
 	input eth_in_e,  // error flag from PHY
@@ -324,7 +324,7 @@ module arp_patt(
 	output pass
 );
 
-reg [7:0] template;
+reg [7:0] template=0;
 always @(posedge clk) case(cnt[3:0])
 	// template starts at 12th byte of Ethernet packet,
 	// after the two MAC addresses.
@@ -362,7 +362,7 @@ module ip_patt(
 	output [15:0] length
 );
 
-reg [7:0] template;
+reg [7:0] template=0;
 always @(posedge clk) case(cnt[4:0])
 	// template starts at 12th byte of Ethernet packet,
 	// after the two MAC addresses.
@@ -441,7 +441,7 @@ module icmp_patt(
 	output pass
 );
 
-reg [7:0] template;
+reg [7:0] template=0;
 always @(posedge clk) case(cnt[2:0])
 	// Ethernet/IP header is not in our scope
 	// template starts at 23rd byte of Ethernet packet,

badger/status.md

@@ -24,23 +24,22 @@ Synthesized by XST 14.7 for Spartan-6:
 
 | **module**         |**LUTs**|**RAMB16**|
 |:-------------------:|:-----:|:--------:|
-|  scanner.v          |  275  |   |
-|  construct.v        |  192  |   |
-|  xformer.v          |   93  |   |
-|  ethernet_crc_add.v |   94  |   |
-|  udp_port_cam_v     |   31  |   |
-|  rtefi_blob.v       | 1024  | 2 |
-|  gmii_hw_test.v     | 1242  | 4 |
+|  scanner.v          |  271  |     |
+|  construct.v        |  192  |     |
+|  xformer.v          |   93  |     |
+|  ethernet_crc_add.v |   94  |     |
+|  udp_port_cam_v     |   31  |     |
+|  rtefi_blob.v       | 1044  |  2  |
+|  gmii_hw_test.v     | 1582  | 6.5 |
 
 This Verilog code is intentionally portable and standards-based.
 It has been tested using:
 
-* verilator 3.900 (stock Debian stretch)
-* verilator 4.008 (git from December 2018)
-* iverilog 10.1 (stock Debian stretch)
-* iverilog 11.0 (git from December 2018)
+* verilator 3.900 through 5.032 (including 5.006 in stock Debian 12 bookworm)
+* iverilog 10.1 through 12.0 (including 11.0 in stock Debian 12 bookworm)
+* yosys 0.23 through 0.52 (including 0.23 in stock Debian 12 bookworm)
 * Xilinx XST 14.7
-* Xilinx Vivado 2015.3, 2017.4, 2018.1
+* Xilinx Vivado 2015.3, 2017.4, 2018.1, 2020.2
 
 All the .eps files here are created with and editable by xcircuit.
 

badger/tests/Makefile

@@ -218,13 +218,13 @@ hw_test_yosys.json: hw_test_skin.v $(HW_TEST_V)
 # experimental bitfiles, not for hardware
 # summarizes fabric footprints based on XST synthesizing for Spartan-6
 bits: scanner.bit construct.bit xformer.bit ethernet_crc_add.bit udp_port_cam_wrap.bit rtefi_blob.bit
-	cd _xilinx && for f in $(basename $^); do echo $$f; grep "Slice LUT" $${f}_map.mrp; done
+	cd _xilinx && for f in $(basename $^); do echo $$f; grep -E "of Slice LUT|of RAMB" $${f}_map.mrp; done
 scanner.bit: ones_chksum.v udp_port_cam.v crc8e_guts.v reg_tech_cdc.v
 construct.bit: ones_chksum.v construct_tx_table.v
 xformer.bit: hack_icmp_cksum.v reg_delay.v
 ethernet_crc_add.bit: crc8e_guts.v
 udp_port_cam_wrap.bit: udp_port_cam.v
-rtefi_blob.bit: $(RTEFI_V)
+rtefi_blob.bit: $(RTEFI_V) rtefi_blob.ucf
 
 # =====
 # Make a bitfile for an SP605 with Xilinx XST

badger/tests/rtefi_blob.ucf

@@ -0,0 +1,6 @@
+NET "rx_clk" LOC="K21";
+NET "rx_clk" TNM_NET = "CLK_1";
+TIMESPEC "TS_CLK_1" = PERIOD "CLK_1" 6.8 ns HIGH 50%;
+NET "tx_clk" LOC="L20";
+NET "tx_clk" TNM_NET = "CLK_2";
+TIMESPEC "TS_CLK_2" = PERIOD "CLK_2" 6.8 ns HIGH 50%;

badger/udp_port_cam.v

@@ -32,7 +32,7 @@
 module udp_port_cam #(
 	parameter naw=3  // address width for abstract port memory
 ) (
-	input clk,
+	input clk,  // timespec 6.8 ns
 	input port_s,
 	input [7:0] data,
 	// port to config memory, single-cycle latency

badger/xformer.v

@@ -2,7 +2,7 @@
 // Uses the rearranged input packet and meta-information
 // to create output packet, still sans CRC32.
 module xformer(
-	input clk,
+	input clk,  // timespec 6.8 ns
 	input [5:0] pc,
 	input [1:0] category,
 	input [2:0] udp_sel,

build-tools/xil_syn

@@ -188,7 +188,7 @@ echo "\`include \"$XILINX/verilog/src/iSE/unisim_comp.v\"" >>"$DESIGN.prj"
 if test -z "$ucf"; then ucf="root/${DESIGN}.ucf"; fi
 if [ ! -r "$ucf" ]; then
     ucf=${DESIGN}.ucf
-    perl -ne 'if (/(\w+)[,;]\s+\/\/ timespec\s+(.+)/) {print "NET \"$1\" LOC=\"'"${CLOCK_PIN}"'\";\nNET \"$1\" TNM_NET = \"CLK_1\";\nTIMESPEC \"TS_CLK_1\" = PERIOD \"CLK_1\" $2 HIGH 50%;\n"}' "root/$toplevel" >"$ucf"
+    perl -ne 'if (/(\w+)[,;]\s+\/\/ timespec\s+(.+)/) {print "NET \"$1\" LOC=\"'"${CLOCK_PIN}"'\";\nNET \"$1\" TNM_NET = \"CLK_1\";\nTIMESPEC \"TS_CLK_1\" = PERIOD \"CLK_1\" $2 HIGH 50%;\n"}' "$toplevel" >"$ucf"
 fi
 test -r "$ucf" || BOMB="$BOMB $ucf"