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rnaxantonblanchard
authored and
Michael Tokarev
committed
target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions
Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Signed-off-by: Max Chou <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> Cc: [email protected] (cherry picked from commit 1f090a2) Signed-off-by: Michael Tokarev <[email protected]>
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-18
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-18
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‎target/riscv/insn_trans/trans_rvbf16.c.inc

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,11 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
119119
REQUIRE_FPU;
120120
REQUIRE_ZVFBFWMA(ctx);
121121

122+
uint8_t sew = ctx->sew;
122123
if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
123-
vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
124+
vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm) &&
125+
vext_check_input_eew(ctx, a->rd, sew + 1, a->rs1, sew, a->vm) &&
126+
vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
124127
uint32_t data = 0;
125128

126129
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
@@ -146,8 +149,10 @@ static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a)
146149
REQUIRE_FPU;
147150
REQUIRE_ZVFBFWMA(ctx);
148151

152+
uint8_t sew = ctx->sew;
149153
if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
150-
vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
154+
vext_check_ds(ctx, a->rd, a->rs2, a->vm) &&
155+
vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
151156
uint32_t data = 0;
152157

153158
gen_set_rm(ctx, RISCV_FRM_DYN);

‎target/riscv/insn_trans/trans_rvv.c.inc

Lines changed: 61 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -528,13 +528,15 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
528528
static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
529529
{
530530
return vext_wide_check_common(s, vd, vm) &&
531+
vext_check_input_eew(s, vs, s->sew, -1, 0, vm) &&
531532
require_align(vs, s->lmul) &&
532533
require_noover(vd, s->lmul + 1, vs, s->lmul);
533534
}
534535

535536
static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
536537
{
537538
return vext_wide_check_common(s, vd, vm) &&
539+
vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm) &&
538540
require_align(vs, s->lmul + 1);
539541
}
540542

@@ -553,6 +555,7 @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
553555
static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
554556
{
555557
return vext_check_ds(s, vd, vs2, vm) &&
558+
vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
556559
require_align(vs1, s->lmul) &&
557560
require_noover(vd, s->lmul + 1, vs1, s->lmul);
558561
}
@@ -575,12 +578,14 @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
575578
static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
576579
{
577580
return vext_check_ds(s, vd, vs1, vm) &&
581+
vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
578582
require_align(vs2, s->lmul + 1);
579583
}
580584

581585
static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
582586
{
583-
bool ret = vext_narrow_check_common(s, vd, vs, vm);
587+
bool ret = vext_narrow_check_common(s, vd, vs, vm) &&
588+
vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm);
584589
if (vd != vs) {
585590
ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
586591
}
@@ -603,6 +608,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
603608
static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
604609
{
605610
return vext_check_sd(s, vd, vs2, vm) &&
611+
vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
606612
require_align(vs1, s->lmul);
607613
}
608614

@@ -1531,6 +1537,16 @@ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
15311537
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
15321538
}
15331539

1540+
/* OPIVV with overwrite and WIDEN */
1541+
static bool opivv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
1542+
{
1543+
return require_rvv(s) &&
1544+
vext_check_isa_ill(s) &&
1545+
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
1546+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
1547+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
1548+
}
1549+
15341550
static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
15351551
gen_helper_gvec_4_ptr *fn,
15361552
bool (*checkfn)(DisasContext *, arg_rmrr *))
@@ -1578,6 +1594,14 @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
15781594
vext_check_ds(s, a->rd, a->rs2, a->vm);
15791595
}
15801596

1597+
static bool opivx_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
1598+
{
1599+
return require_rvv(s) &&
1600+
vext_check_isa_ill(s) &&
1601+
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
1602+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
1603+
}
1604+
15811605
#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
15821606
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
15831607
{ \
@@ -2049,13 +2073,13 @@ GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
20492073
GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
20502074

20512075
/* Vector Widening Integer Multiply-Add Instructions */
2052-
GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
2053-
GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
2054-
GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
2055-
GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
2056-
GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
2057-
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
2058-
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
2076+
GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_overwrite_widen_check)
2077+
GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_overwrite_widen_check)
2078+
GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_overwrite_widen_check)
2079+
GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_overwrite_widen_check)
2080+
GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_overwrite_widen_check)
2081+
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_overwrite_widen_check)
2082+
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_overwrite_widen_check)
20592083

20602084
/* Vector Integer Merge and Move Instructions */
20612085
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
@@ -2396,6 +2420,17 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
23962420
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
23972421
}
23982422

2423+
static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
2424+
{
2425+
return require_rvv(s) &&
2426+
require_rvf(s) &&
2427+
require_scale_rvf(s) &&
2428+
vext_check_isa_ill(s) &&
2429+
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
2430+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
2431+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
2432+
}
2433+
23992434
/* OPFVV with WIDEN */
24002435
#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
24012436
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
@@ -2435,6 +2470,16 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
24352470
vext_check_ds(s, a->rd, a->rs2, a->vm);
24362471
}
24372472

2473+
static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
2474+
{
2475+
return require_rvv(s) &&
2476+
require_rvf(s) &&
2477+
require_scale_rvf(s) &&
2478+
vext_check_isa_ill(s) &&
2479+
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
2480+
vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
2481+
}
2482+
24382483
/* OPFVF with WIDEN */
24392484
#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
24402485
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
@@ -2559,14 +2604,14 @@ GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
25592604
GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
25602605

25612606
/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
2562-
GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
2563-
GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
2564-
GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
2565-
GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
2566-
GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
2567-
GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
2568-
GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
2569-
GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
2607+
GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check)
2608+
GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check)
2609+
GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check)
2610+
GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check)
2611+
GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check)
2612+
GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check)
2613+
GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check)
2614+
GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check)
25702615

25712616
/* Vector Floating-Point Square-Root Instruction */
25722617

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