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qtouch: switch PTC to 8Mhz clock from 12 Mhz
8Mhz is recommended by the tooling and can be divided down to the required 2Mhz with the ADC prescaler
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2 files changed

+6
-6
lines changed

2 files changed

+6
-6
lines changed

external/asf4-drivers/Config/hpl_gclk_config.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -387,7 +387,7 @@
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// <i> Indicates whether generic clock 5 configuration is enabled or not
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// <id> enable_gclk_gen_5
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#ifndef CONF_GCLK_GENERATOR_5_CONFIG
390-
#define CONF_GCLK_GENERATOR_5_CONFIG 0
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#define CONF_GCLK_GENERATOR_5_CONFIG 1
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#endif
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// <h> Generic Clock Generator Control
@@ -404,7 +404,7 @@
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// <i> This defines the clock source for generic clock generator 5
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// <id> gclk_gen_5_oscillator
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#ifndef CONF_GCLK_GEN_5_SOURCE
407-
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_GCLKGEN1
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#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL
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#endif
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// <q> Run in Standby
@@ -446,15 +446,15 @@
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_5_enable
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#ifndef CONF_GCLK_GEN_5_GENEN
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#define CONF_GCLK_GEN_5_GENEN 0
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#define CONF_GCLK_GEN_5_GENEN 1
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 5 division <0x0000-0xFFFF>
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// <id> gclk_gen_5_div
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#ifndef CONF_GCLK_GEN_5_DIV
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#define CONF_GCLK_GEN_5_DIV 62
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#define CONF_GCLK_GEN_5_DIV 6
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#endif
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// </h>
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// </e>

external/asf4-drivers/Config/peripheral_clk_config.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,15 +33,15 @@
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// <i> Select the clock source for ADC.
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#ifndef CONF_GCLK_ADC0_SRC
36-
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
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#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK5_Val
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#endif
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/**
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* \def CONF_GCLK_ADC0_FREQUENCY
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* \brief ADC0's Clock frequency
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*/
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#ifndef CONF_GCLK_ADC0_FREQUENCY
44-
#define CONF_GCLK_ADC0_FREQUENCY 12000000
44+
#define CONF_GCLK_ADC0_FREQUENCY 8000000
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#endif
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/**

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