asf4 config: Activate clock generator 5

Activate an unused clock generator with source DFLL (48Mhz) and divisor
6 to generate 8Mhz. This is useful for running ADCs (max frequency for
ADC) and for running the sd-card clock that otherwise introduces a lot
of noise to the ADC. The ADC is what measures touch.

Author: NickeZ

external/asf4-drivers/Config/hpl_gclk_config.h

@@ -387,7 +387,7 @@
 // <i> Indicates whether generic clock 5 configuration is enabled or not
 // <id> enable_gclk_gen_5
 #ifndef CONF_GCLK_GENERATOR_5_CONFIG
-#define CONF_GCLK_GENERATOR_5_CONFIG 0
+#define CONF_GCLK_GENERATOR_5_CONFIG 1
 #endif
 
 // <h> Generic Clock Generator Control
@@ -404,7 +404,7 @@
 // <i> This defines the clock source for generic clock generator 5
 // <id> gclk_gen_5_oscillator
 #ifndef CONF_GCLK_GEN_5_SOURCE
-#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_GCLKGEN1
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL
 #endif
 
 // <q> Run in Standby
@@ -446,15 +446,15 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_5_enable
 #ifndef CONF_GCLK_GEN_5_GENEN
-#define CONF_GCLK_GEN_5_GENEN 0
+#define CONF_GCLK_GEN_5_GENEN 1
 #endif
 // </h>
 
 //<h> Generic Clock Generator Division
 //<o> Generic clock generator 5 division <0x0000-0xFFFF>
 // <id> gclk_gen_5_div
 #ifndef CONF_GCLK_GEN_5_DIV
-#define CONF_GCLK_GEN_5_DIV 62
+#define CONF_GCLK_GEN_5_DIV 6
 #endif
 // </h>
 // </e>