add configuration for SPI_MEM

CLOCKS:
- SPI_MEM Core CLK: generic 0 (120MHz)
- SPI_MEM Slow CLK: generic 3 (48MHz)
- Sercom baud rate: 8MHz

The MX25 module needs 80MHz for high performance mode and 8MHz in low
power. Since the minimum divider for the baud rate generator is 4 (with
BAUD reg set to 1, see 33.6.2.3 of SAM D5 datasheet), we need an input
clock of 320MHz in high performance, which is not achievable with our
mcu. We'll go with the low-power mode.

I am not sure we actually need the low power clock.

PORTS:
Enabled SPI_MEM interface on SERCOM4 with the following pinout:
- CLK -> PA12
- MOSI -> PA15
- MISO -> PA13
- CS -> PA14
- WP -> PB07
- HOLD -> PA20

The code has been originally generated using the Atmel start tool and
adapted to the project.

Author: Beerosagos

external/asf4-drivers/Config/peripheral_clk_config.h

@@ -95,6 +95,86 @@
 
 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
 
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM4_CORE_SRC
+#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
+#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
+ * \brief SERCOM4's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 120000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+ * \brief SERCOM4's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 48000000
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
 // <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM3_CORE_SRC
 #define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val

external/asf4-drivers/hpl/spi/spi_lite.c

@@ -35,6 +35,129 @@
 #include "spi_lite.h"
 #include <utils_assert.h>
 
+/**
+ * \brief Initialize SPI interface
+ */
+int8_t SPI_MEM_init(void)
+{
+	if (!hri_sercomspi_is_syncing(SERCOM4, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		uint32_t mode = SERCOM_SPI_CTRLA_MODE(3);
+		if (hri_sercomspi_get_CTRLA_reg(SERCOM4, SERCOM_SPI_CTRLA_ENABLE)) {
+			hri_sercomspi_clear_CTRLA_ENABLE_bit(SERCOM4);
+			hri_sercomspi_wait_for_sync(SERCOM4, SERCOM_SPI_SYNCBUSY_ENABLE);
+		}
+		hri_sercomspi_write_CTRLA_reg(SERCOM4, SERCOM_SPI_CTRLA_SWRST | mode);
+	}
+	hri_sercomspi_wait_for_sync(SERCOM4, SERCOM_SPI_SYNCBUSY_SWRST);
+
+	hri_sercomspi_write_CTRLA_reg(
+	    SERCOM4,
+	    0 << SERCOM_SPI_CTRLA_DORD_Pos           /* Data Order: disabled */
+	        | 0 << SERCOM_SPI_CTRLA_CPOL_Pos     /* Clock Polarity: disabled */
+	        | 0 << SERCOM_SPI_CTRLA_CPHA_Pos     /* Clock Phase: disabled */
+	        | 0 << SERCOM_SPI_CTRLA_FORM_Pos     /* Frame Format: 0 */
+	        | 0 << SERCOM_SPI_CTRLA_IBON_Pos     /* Immediate Buffer Overflow Notification: disabled */
+	        | 0 << SERCOM_SPI_CTRLA_RUNSTDBY_Pos /* Run In Standby: disabled */
+	        | 3 << SERCOM_SPI_CTRLA_MODE_Pos);   /* Operating Mode: 3 */
+
+	hri_sercomspi_write_CTRLA_DOPO_bf(SERCOM4, SERCOM4_TXPO);
+	hri_sercomspi_write_CTRLA_DIPO_bf(SERCOM4, SERCOM4_RXPO);
+
+	hri_sercomspi_write_CTRLB_reg(SERCOM4,
+	                              1 << SERCOM_SPI_CTRLB_RXEN_Pos          /* Receiver Enable: enabled */
+	                                  | 0 << SERCOM_SPI_CTRLB_MSSEN_Pos   /* Master Slave Select Enabl: disabled */
+	                                  | 0 << SERCOM_SPI_CTRLB_AMODE_Pos   /* Address Mode: 0 */
+	                                  | 0 << SERCOM_SPI_CTRLB_SSDE_Pos    /* Slave Select Low Detect Enable: disabled */
+	                                  | 0 << SERCOM_SPI_CTRLB_PLOADEN_Pos /* Slave Data Preload Enable: disabled */
+	                                  | 0);                               /* Character Size: 0 */
+
+	hri_sercomspi_write_BAUD_reg(SERCOM4, SERCOM4_BAUD_RATE);
+
+	// hri_sercomspi_write_DBGCTRL_reg(SERCOM4,0 << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos); /* Debug Stop Mode: disabled */
+
+	// hri_sercomspi_write_INTEN_reg(SERCOM4,0 << SERCOM_SPI_INTENSET_ERROR_Pos /* Error Interrupt Enable: disabled */
+	//		 | 0 << SERCOM_SPI_INTENSET_SSL_Pos /* Slave Select Low Interrupt Enable: disabled */
+	//		 | 0 << SERCOM_SPI_INTENSET_RXC_Pos /* Receive Complete Interrupt Enable: disabled */
+	//		 | 0 << SERCOM_SPI_INTENSET_TXC_Pos /* Transmit Complete Interrupt Enable: disabled */
+	//		 | 0 << SERCOM_SPI_INTENSET_DRE_Pos); /* Data Register Empty Interrupt Enable: disabled */
+
+	hri_sercomspi_write_CTRLA_ENABLE_bit(SERCOM4, 1 << SERCOM_SPI_CTRLA_ENABLE_Pos); /* Enable: enabled */
+
+	return 0;
+}
+
+/**
+ * \brief Enable SPI module
+ */
+void SPI_MEM_enable(void)
+{
+	hri_sercomspi_set_CTRLA_ENABLE_bit(SERCOM4);
+}
+
+/**
+ * \brief Disable SPI module
+ */
+void SPI_MEM_disable(void)
+{
+	hri_sercomspi_clear_CTRLA_ENABLE_bit(SERCOM4);
+}
+
+/**
+ * \brief Exchange_byte in SPI module
+ */
+uint32_t SPI_MEM_exchange_data(uint32_t data)
+{
+	/* If settings are not applied (pending), we can not go on */
+	if (hri_sercomspi_is_syncing(
+	        SERCOM4, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_write_DATA_reg(SERCOM4, data);
+	while (!(hri_sercomspi_read_INTFLAG_reg(SERCOM4) & SERCOM_SPI_INTFLAG_RXC))
+		;
+	return hri_sercomspi_read_DATA_reg(SERCOM4);
+}
+
+void SPI_MEM_exchange_block(void *block, uint8_t size)
+{
+
+	uint8_t *b = (uint8_t *)block;
+
+	while (size--) {
+		hri_sercomspi_write_DATA_reg(SERCOM4, *b);
+		while (!(hri_sercomspi_read_INTFLAG_reg(SERCOM4) & SERCOM_SPI_INTFLAG_RXC))
+			;
+		*b = hri_sercomspi_read_DATA_reg(SERCOM4);
+		b++;
+	}
+}
+
+void SPI_MEM_write_block(void *block, uint8_t size)
+{
+
+	uint8_t *b = (uint8_t *)block;
+	while (size--) {
+		hri_sercomspi_write_DATA_reg(SERCOM4, *b);
+		while (!(hri_sercomspi_read_INTFLAG_reg(SERCOM4) & SERCOM_SPI_INTFLAG_RXC))
+			;
+		b++;
+	}
+}
+
+void SPI_MEM_read_block(void *block, uint8_t size)
+{
+
+	uint8_t *b = (uint8_t *)block;
+	while (size--) {
+		hri_sercomspi_write_DATA_reg(SERCOM4, 0);
+		while (!(hri_sercomspi_read_INTFLAG_reg(SERCOM4) & SERCOM_SPI_INTFLAG_RXC))
+			;
+		*b = hri_sercomspi_read_DATA_reg(SERCOM4);
+		b++;
+	}
+}
+
 /**
  * \brief Initialize SPI interface
  */

external/asf4-drivers/hpl/spi/spi_lite.h

@@ -51,9 +51,59 @@
 extern "C" {
 #endif
 
+// Calculate baud register value from requested baudrate value
+#ifndef SERCOM4_BAUD_RATE
+#define SERCOM4_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * 8000000)) - 1
+#endif
+
+#ifndef SERCOM4_RXPO
+#define SERCOM4_RXPO 0
+#endif
+
+#ifndef SERCOM4_TXPO
+#define SERCOM4_TXPO 2
+#endif
+
+/**
+ * \brief Initialize usart interface
+ *
+ * \return Initialization status.
+ */
+int8_t SPI_MEM_init(void);
+
+/**
+ * \brief Enable SPI module
+ */
+void SPI_MEM_enable(void);
+
+/**
+ * \brief Disable SPI module
+ */
+void SPI_MEM_disable(void);
+
+/**
+ * \brief Exchange byte in SPI module
+ */
+uint32_t SPI_MEM_exchange_data(uint32_t data);
+
+/**
+ * \brief Exchange block in SPI module
+ */
+void SPI_MEM_exchange_block(void *block, uint8_t size);
+
+/**
+ * \brief Write block in SPI module
+ */
+void SPI_MEM_write_block(void *block, uint8_t size);
+
+/**
+ * \brief Read block in SPI module
+ */
+void SPI_MEM_read_block(void *block, uint8_t size);
+
 // Calculate baud register value from requested baudrate value
 #ifndef SERCOM3_BAUD_RATE
-#define SERCOM3_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * 3000000)) - 1
+#define SERCOM3_BAUD_RATE (((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * 3000000)) - 1)
 #endif
 
 #ifndef SERCOM3_RXPO

src/platform/bitbox02_pins.h

@@ -28,6 +28,12 @@
 #define PIN_SPI_MOSI GPIO(GPIO_PORTA, 17)
 #define PIN_SPI_MISO GPIO(GPIO_PORTA, 18)
 #define PIN_OLED_CS GPIO(GPIO_PORTA, 19)
+#define PIN_MEM_CLK GPIO(GPIO_PORTA, 12)
+#define PIN_MEM_MOSI GPIO(GPIO_PORTA, 15)
+#define PIN_MEM_MISO GPIO(GPIO_PORTA, 13)
+#define PIN_MEM_CS GPIO(GPIO_PORTA, 14)
+#define PIN_MEM_HOLD GPIO(GPIO_PORTA, 20)
+#define PIN_MEM_WP GPIO(GPIO_PORTB, 7)
 #define PIN_I2C_SCL GPIO(GPIO_PORTA, 22)
 #define PIN_I2C_SDA GPIO(GPIO_PORTA, 23)
 #define PIN_USB_DM GPIO(GPIO_PORTA, 24)

src/platform/driver_init.c

@@ -15,6 +15,12 @@
 // THIS IS A GENERATED FILE, MODIFY AS LITTLE AS POSSIBLE
 
 #include "driver_init.h"
+#include "bitbox02_pins.h"
+#include "memory/memory_shared.h"
+#include "util.h"
+#include <compiler.h>
+#include <hal_sleep.h>
+#include <stdint.h>
 #include <utils.h>
 
 #define PIN_HIGH 1
@@ -115,6 +121,57 @@ static void _spi_init(void)
     SPI_OLED_enable();
 }
 
+static void _spi_mem_clock_init(void)
+{
+    hri_gclk_write_PCHCTRL_reg(
+        GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+    hri_gclk_write_PCHCTRL_reg(
+        GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+    hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
+}
+
+static void _spi_mem_port_init(void)
+{
+    // CS
+    gpio_set_pin_level(PIN_MEM_CS, PIN_LOW);
+    gpio_set_pin_direction(PIN_MEM_CS, GPIO_DIRECTION_OUT);
+    gpio_set_pin_function(PIN_MEM_CS, GPIO_PIN_FUNCTION_OFF);
+
+    // MISO
+    gpio_set_pin_direction(PIN_MEM_MISO, GPIO_DIRECTION_IN);
+    gpio_set_pin_pull_mode(PIN_MEM_MISO, GPIO_PULL_OFF);
+    gpio_set_pin_function(PIN_MEM_MISO, PINMUX_PA13D_SERCOM4_PAD0);
+
+    // CLK
+    gpio_set_pin_level(PIN_MEM_CLK, PIN_LOW);
+    gpio_set_pin_direction(PIN_MEM_CLK, GPIO_DIRECTION_OUT);
+    gpio_set_pin_function(PIN_MEM_CLK, PINMUX_PA12D_SERCOM4_PAD1);
+
+    // MOSI
+    gpio_set_pin_level(PIN_MEM_MOSI, PIN_LOW);
+    gpio_set_pin_direction(PIN_MEM_MOSI, GPIO_DIRECTION_OUT);
+    gpio_set_pin_function(PIN_MEM_MOSI, PINMUX_PA15D_SERCOM4_PAD3);
+
+    // HOLD
+    gpio_set_pin_level(PIN_MEM_HOLD, PIN_HIGH);
+    gpio_set_pin_direction(PIN_MEM_HOLD, GPIO_DIRECTION_OUT);
+
+    // WP
+    gpio_set_pin_level(PIN_MEM_WP, PIN_HIGH);
+    gpio_set_pin_direction(PIN_MEM_WP, GPIO_DIRECTION_OUT);
+}
+
+/**
+ * Initialize SPI 1 peripheral
+ */
+static void _spi_mem_init(void)
+{
+    _spi_mem_clock_init();
+    SPI_MEM_init();
+    _spi_mem_port_init();
+}
+
 /**
  * Set pins for I2C peripheral
  */
@@ -300,6 +357,12 @@ void system_init(void)
     _flash_memory_init();
     // USB
     _usb_init();
+
+    if (memory_get_platform() == MEMORY_PLATFORM_BITBOX02_PLUS) {
+        // External MX25 flash memory
+        _spi_mem_init();
+    }
+
     _is_initialized = true;
 }
 
@@ -325,6 +388,12 @@ void bootloader_init(void)
     _flash_memory_init();
     // USB
     _usb_init();
+
+    if (memory_get_platform() == MEMORY_PLATFORM_BITBOX02_PLUS) {
+        // External MX25 flash memory
+        _spi_mem_init();
+    }
+
     _is_initialized = true;
 }