Refactoring of nrn_setup.cpp in separate phases (phase1.cpp / phase2.cpp) (#283)

Major refactoring of monolithic nrn_setup.cpp into two separate phases that allows to
re-use the code for file based transfer as well as memory transfer:
 * Rewrite phase1, phase2 and move into separate .cpp files
 * Remove global static user variables
 * Add OMP_Mutex wrapper for handling OpenMP mutex
 * VecPlay now use std::vector instead of raw pointers
     - Give ownership of y_, t_ to VecPlayContinuous
 * Remove lock / unlock from fixed_vector as it was not used 
 * Remove things related to endianess : code as well as tests
 * Use name of phase instead of numbers with template arguments
* Check mechanism compatibility before reading data
   - if mechanism / mod file is different, we can't read data
     because sizes between neuron and coreneuron will be different.
     This will result into segfault / memory error.
  - check mechanism compatibility right after mechanism information
     is available

Co-authored-by: Omar Awile <[email protected]>
Co-authored-by: pramodk <[email protected]>

Thanks @alkino for major work!

Author: Nicolas Cornu

CMake/ClangFormatHelper.cmake

@@ -23,12 +23,6 @@ if(CLANG_FORMAT_FOUND)
                     ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/*.h*
                     ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/*.ipp*)
 
-  # exclude ezoption headers
-  list(REMOVE_ITEM SRC_FILES_FOR_CLANG_FORMAT
-                   ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/utils/ezoption/ezOptionParser.hpp
-                   ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/utils/endianness.h
-                   ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/utils/swap_endian.h)
-
   # exclude random123
   file(GLOB_RECURSE RANDOM123_FILES
                     ${CORENEURON_PROJECT_SOURCE_DIR}/coreneuron/utils/randoms/Random123/*.cpp

coreneuron/apps/main1.cpp

@@ -603,7 +603,7 @@ extern "C" int run_solve_core(int argc, char** argv) {
 
     {
         Instrumentor::phase p("checkpoint");
-        write_checkpoint(nrn_threads, nrn_nthread, corenrn_param.checkpointpath.c_str(), nrn_need_byteswap);
+        write_checkpoint(nrn_threads, nrn_nthread, corenrn_param.checkpointpath.c_str());
     }
 
     // must be done after checkpoint (to avoid deleting events)

coreneuron/gpu/nrn_acc_manager.cpp

@@ -22,7 +22,7 @@
 #endif
 namespace coreneuron {
 extern InterleaveInfo* interleave_info;
-void copy_ivoc_vect_to_device(IvocVect*& iv, IvocVect*& div);
+void copy_ivoc_vect_to_device(const IvocVect& iv, IvocVect& div);
 void nrn_ion_global_map_copyto_device();
 void nrn_VecPlay_copyto_device(NrnThread* nt, void** d_vecplay);
 
@@ -389,21 +389,19 @@ void setup_nrnthreads_on_device(NrnThread* threads, int nthreads) {
 #endif
 }
 
-void copy_ivoc_vect_to_device(IvocVect*& iv, IvocVect*& div) {
+void copy_ivoc_vect_to_device(const IvocVect& from, IvocVect& to) {
 #ifdef _OPENACC
-    if (iv) {
-        IvocVect* d_iv = (IvocVect*)acc_copyin(iv, sizeof(IvocVect));
-        acc_memcpy_to_device(&div, &d_iv, sizeof(IvocVect*));
-
-        size_t n = iv->size();
-        if (n) {
-            double* d_data = (double*)acc_copyin(iv->data(), sizeof(double) * n);
-            acc_memcpy_to_device(&(d_iv->data_), &d_data, sizeof(double*));
-        }
+    IvocVect* d_iv = (IvocVect*)acc_copyin((void*)&from, sizeof(IvocVect));
+    acc_memcpy_to_device(&to, d_iv, sizeof(IvocVect));
+
+    size_t n = from.size();
+    if (n) {
+        double* d_data = (double*)acc_copyin((void*)from.data(), sizeof(double) * n);
+        acc_memcpy_to_device(&(d_iv->data_), &d_data, sizeof(double*));
     }
 #else
-    (void)iv;
-    (void)div;
+    (void)from;
+    (void)to;
 #endif
 }
 
@@ -1004,8 +1002,10 @@ void nrn_VecPlay_copyto_device(NrnThread* nt, void** d_vecplay) {
         /** copy y_, t_ and discon_indices_ */
         copy_ivoc_vect_to_device(vecplay_instance->y_, d_vecplay_instance->y_);
         copy_ivoc_vect_to_device(vecplay_instance->t_, d_vecplay_instance->t_);
-        copy_ivoc_vect_to_device(vecplay_instance->discon_indices_,
-                                 d_vecplay_instance->discon_indices_);
+        if (vecplay_instance->discon_indices_) {
+            copy_ivoc_vect_to_device(*(vecplay_instance->discon_indices_),
+                                 *(d_vecplay_instance->discon_indices_));
+         }
 
         /** copy PlayRecordEvent : todo: verify this */
         PlayRecordEvent* d_e_ =

coreneuron/io/mem_layout_util.cpp

@@ -0,0 +1,56 @@
+#include "mem_layout_util.hpp"
+
+namespace coreneuron {
+
+/// calculate size after padding for specific memory layout
+// Warning: this function is declared extern in nrniv_decl.h
+int nrn_soa_padded_size(int cnt, int layout) {
+    return soa_padded_size<NRN_SOA_PAD>(cnt, layout);
+}
+
+/// return the new offset considering the byte aligment settings
+size_t nrn_soa_byte_align(size_t size) {
+    if (LAYOUT == Layout::SoA) {
+        size_t dbl_align = NRN_SOA_BYTE_ALIGN / sizeof(double);
+        size_t remainder = size % dbl_align;
+        if (remainder) {
+            size += dbl_align - remainder;
+        }
+        nrn_assert((size * sizeof(double)) % NRN_SOA_BYTE_ALIGN == 0);
+    }
+    return size;
+}
+
+int nrn_i_layout(int icnt, int cnt, int isz, int sz, int layout) {
+    switch(layout) {
+      case Layout::AoS:
+        return icnt * sz + isz;
+      case Layout::SoA:
+        int padded_cnt = nrn_soa_padded_size(cnt, layout);  // may want to factor out to save time
+        return icnt + isz * padded_cnt;
+    }
+
+    nrn_assert(false);
+    return 0;
+}
+
+// file data is AoS. ie.
+// organized as cnt array instances of mtype each of size sz.
+// So input index i refers to i_instance*sz + i_item offset
+// Return the corresponding SoA index -- taking into account the
+// alignment requirements. Ie. i_instance + i_item*align_cnt.
+
+int nrn_param_layout(int i, int mtype, Memb_list* ml) {
+    int layout = corenrn.get_mech_data_layout()[mtype];
+    switch(layout) {
+      case Layout::AoS:
+        return i;
+      case Layout::SoA:
+        nrn_assert(layout == Layout::SoA);
+        int sz = corenrn.get_prop_param_size()[mtype];
+        return nrn_i_layout(i / sz, ml->nodecount, i % sz, sz, layout);
+    }
+    nrn_assert(false);
+    return 0;
+}
+}  // namespace coreneuron

coreneuron/io/mem_layout_util.hpp

@@ -0,0 +1,45 @@
+#pragma once
+
+#include "coreneuron/coreneuron.hpp"
+#include "coreneuron/nrniv/nrniv_decl.h"
+
+namespace coreneuron {
+
+#if !defined(NRN_SOA_PAD)
+// for layout 0, every range variable array must have a size which
+// is a multiple of NRN_SOA_PAD doubles
+#define NRN_SOA_PAD 8
+#endif
+
+// If MATRIX_LAYOUT is 1 then a,b,d,rhs,v,area is not padded using NRN_SOA_PAD
+// When MATRIX_LAYOUT is 0 then mechanism pdata index values into _actual_v
+// and _actual_area data need to be updated.
+enum Layout {
+    SoA = 0,
+    AoS = 1
+};
+
+#if !defined(LAYOUT)
+#define LAYOUT Layout::AoS
+#define MATRIX_LAYOUT Layout::AoS
+#else
+#define MATRIX_LAYOUT LAYOUT
+#endif
+
+/// return the new offset considering the byte aligment settings
+size_t nrn_soa_byte_align(size_t i); 
+
+/// This function return the index in a flat array of a matrix coordinate (icnt, isz).
+/// The matrix size is (cnt, sz)
+/// Depending of the layout some padding can be calculated
+int nrn_i_layout(int icnt, int cnt, int isz, int sz, int layout);
+
+// file data is AoS. ie.
+// organized as cnt array instances of mtype each of size sz.
+// So input index i refers to i_instance*sz + i_item offset
+// Return the corresponding SoA index -- taking into account the
+// alignment requirements. Ie. i_instance + i_item*align_cnt.
+
+int nrn_param_layout(int i, int mtype, Memb_list* ml);
+}  // namespace coreneuron
+