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Thanks for sharing. Nicely done! |
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I've made another measurement on T-Display-S3, hoping to take advantage of having access to two distinct memory devices, internal RAM and PSRAM with separate data paths, but the improvement was not as expected, only about 2.5 fps from 37 to 39.5. When allocating one sprite from internal RAM and the other one from PSRAM, we can avoid both CPUs having to access the same memory device at the same time, the sequence is like: phase 1: CPU1 writes to internal RAM, and in parallel CPU0 reads from PSRAM and writes to TFT. To force allocation from internal RAM I've called setAttribute(PSRAM_ENABLE, false) for one sprite, and replaced |
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Here is an updated example from the library that moves sprite drawing to the second CPU core, helpful on configurations where DMA is not implemented.
Tested on LilyGO T-Display-S3 and Waveshare RP2040 LCD 1.28".
There are two switches that can be set in the sketch,
USE_SECOND_CORE
andUSE_DMA
, to either0
or1
. If the configuration doesn't have DMA implemented there will be a linker error if the switch is set.On T-Display-S3 without using second core the sketch reports 26.5fps, and when using second core it is 35.5fps.
On RP2040 with dma=0 and multicore=1 the performance is about the same as with dma=1 and multicore=0. When both are set, the sketch doesn't wait for DMA to finish, so the user can visualize what happens when a resource (the sprite) is not guarded against simultaneous access.
On RP2040 calling the TFT from the second core didn't work, probably due to the SPI being initialized on the first core, so I have moved the sprite drawing (
drawUpdate
) on the second core instead, and kept the TFT operations (pushUpdate
) on the first core.(edited for minor name changes and code flow)
Bouncy_Circles_SMP.ino
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