FPGA Hardware Acceleration of 3D reconstruction of EEG data #4
Description
Title
FPGA Hardware Acceleration of 3D reconstruction of EEG data
Leaders
Hossen Alyazgi — [email protected] — cristo07847
Collaborators
No response
Project Description
What is being done, for whom, and why?
This project will aim to apply Hardware Acceleration to the algorithims responsible for the 3D-reconsttruction of EEG signals from the BRAINSTORM Software (GitHub repo).
This hopes to be a Proof of Concept for opening further research avenues into the topic of Closed-Loop Neuromodulation. State-Dependent Neuromodulation requires Real-time feedback of neural signal responses to stimulation, which an FPGA would enable. Initially, this 3D reconstruction could be used to visualize EEG responses in real time for research or clinical use.
Ultimately, the idea however is to leverage the generated topography of 3D EEG activity for use as a structural "prior" to be then fed into Deep-Learning models for extrapolation or inferring connections based on eeg data.
For the BRAINSTORM Project Itself, there have been discussion threads from users who are looking for real time processing options:
Where do I find the option to connect Brainstorm to a live EEG amplifier? (2025)
Real Time Processing in Brain storm (2014)
so there is a desire to have such functionality available. Further reading and research is available in the repo wiki (TBD)
What makes the project special and exciting?
Multimodal neuroimaging is a very exciting domain of research. Electroencephalography (EEG), Magnetoencephalography (MEG), and Functional Near-Infrared Spectroscopy (fNIRS) are noninvasive imaging techniques which all have very high temporal resolution (temporal = high sample rate, which can better be correlated with brain activity) but low spatial resolution (we can't pinpoint as precisely where the signals are coming from as compared to an MRI for example). Combining these imaging techniques, however, results in a fuller picture of what is going on in the brain. This takes the form of using post-processing software and toolboxes such as BRAINSTORM. This however is done after the fact.
The idea behind between accelerating computation of these data processing techniques is to open further possibilites for research and clinical domains, and allow for further vectors of analysis. Normally, the use of integrated circuits and FPGA's in neural processing occurs with invasive methodologies, but for noninvasive approaches this is still type of approach is still open for exploration.
How to get started?
The project is going to be implemented on a DE1-SoC development board. The tentative outline for what needs to be done is on the GitHub ReadMe and will be updated. The plan is to divide work into isolated "chunks" with well defined input -> output files/format and expectations for datatypes and other metrics so that contributors can make their own unit tests and verify functionality
Where to find key resources?
In the GitHub repo (specific locations TBD will be included in ReadMe
Link to project repository/sources
https://github.com/balzacbabylon/neuro-rtl
Goals for Brainhack Montreal
Note: this structure and goals are tentative and subject to change. In particular, the method for vizualization might change as details of the implementation are ironed out.
Day 1: Basic Opeation and Data Pipeline
Goal: Get data flowing from PC to the board and verify the math in software.
Beginner Contributors (Data Prep):
- Task: Install Brainstorm on a laptop. Export the ImagingKernel and a sample EEG recording.
- Task: Write a Python/Matlab script to "simulate" the FPGA: Load the EEG data, multiply by the matrix, and verify the result. This creates the "Golden Vectors" for testing.
Intermediate Contributors (Linux):
- Task: Flash the DE1-SoC SD card with Linux. Get SSH working.
- Task: Write a simple C program on the HPS (ARM) that reads a dummy binary file and prints it to the terminal.
Advanced Contributors (Quartus):
- Task: Set up the Qsys project. Instantiate the HPS system, the SDRAM controller, and a basic LED PIO (Parallel I/O) to prove the HPS can blink an FPGA LED.
Day 2: Core Logic
Goal: Implement the math on hardware and establish the visualization.
Beginner Contributors (Visualization):
- Task: Write the Matlab UDP listener. Make a 3D brain mesh light up with random colors to prove the graphics pipeline works.
Intermediate Contributors (Bridge):
- Task: Expand the C program. Map the HPS-to-FPGA Lightweight Bridge.
- Task: Write the code to "feed" the FPGA: Push one vector of EEG data into a FIFO every 2ms.
Advanced Contributors (DSP):
- Task: Write the Verilog for the Matrix-Vector Multiplier.
- Task: Implement the State Machine
- Constraint: Get the design to compile and fit in the FPGA.
Day 3: Integration
Goal: Merge independent subsystems into a closed loop (Data → HPS → FPGA → HPS → PC).
Beginner Contributors (Data & Visualization)
- Task: Ensure the visualization on the PC accurately reflects the data sent by the board.
- Task: Hardcode a static "Test Pattern" (e.g., Scout 1 = 100%, others = 0%) in the receiving script. Verify that the correct anatomical region lights up before connecting to the live stream.
Intermediate Contributors (Software & Transport)
- Task: Guarantee data integrity between the HPS (ARM) and the PC. Ensure that the UDP packets arrive in the correct order and with the correct byte alignment
- Task: Use tcpdump or Wireshark to prove packets are leaving the board at the correct rate (500Hz). Confirm the payload size matches exactly 68×4 bytes (plus header).
Advanced Contributors (FPGA & Hardware)
- Task: Prove the FPGA is actually doing the work. The output from the hardware registers must match the "Golden Vectors" (simulated results) exactly.
- Task: manually write a single input vector to the FPGA and read the result. Compare this static result against the calculated value from Day 1 to sign off on hardware accuracy.
Skills
Skill Requirements & Prerequisites
| Skill Domain | Beginner | Intermediate | Advanced |
|---|---|---|---|
| FPGA / HDL | Understanding of logic gates, binary math | Verilog/VHDL syntax, Finite State Machines (FSM) | AXI Bus protocols, DSP slice optimization |
| Software | Python (NumPy), Matlab basics | C/C++ (Pointers, structs), Linux basics | Embedded Linux (drivers, mmap), Multi-threading, Network programming |
| Neuroscience | Basic anatomy (lobes of the brain) | Understanding of EEG arrays (10-20 system) | Inverse problems (MNE), Coordinate systems (MNI vs. SCS) |
| Tools | Git, SSH, VS Code | Intel Quartus (Basic flow), Qsys/Platform Designer | SignalTap Logic Analyzer, ModelSim/Questasim |
Tech stack
-
Hardware Layer
Development Board: Terasic DE1-SoC (Cyclone V SoC).
FPGA Fabric: Intel Cyclone V 5CSEMA5 (85K Logic Elements, 4,450 Kbits Embedded Memory, 87 DSP Blocks).
Hard Processor System (HPS): Dual-Core ARM Cortex-A9 MPCore (running at ~800 MHz).
Memory:
FPGA: On-Chip M10K Blocks (BRAM) for storing the ImagingKernel and Lookup Tables. HPS: 1GB DDR3 SDRAM (Shared via AXI bridges if needed).Peripherals:
Ethernet (RJ45): For UDP streaming to the Host PC. SD Card: Boot medium for Linux and storage for the EEG recording file. -
FPGA Design Layer
IDE / Synthesis: Intel Quartus Prime Lite Edition (v18.1 or later recommended).
System Integration: Platform Designer (for connecting the ARM processor to the FPGA logic via AXI bridges)
HDL Language: SystemVerilog
IP Cores (Intel Library):
Altera PLL: To generate system clocks. On-Chip Memory (RAM or ROM): Dual-port configuration. FIFO: For buffering data between HPS and FPGA.Simulation: ModelSim
-
Embedded Software Layer
Operating System: Linux
Language: C/C++ (standard GCC toolchain arm-linux-gnueabihf).
Key Libraries:
mman.h: For memory mapping (mmap) physical addresses to user space (to talk to the FPGA). sys/socket.h: For creating the UDP socket. pthread.h: Seperate threads for FPGA/network data communicationDrivers: Standard Linux /dev/mem interface
-
Host PC Layer
Core Software: Brainstorm3 (running on MATLAB).
Scripting: MATLAB
Networking: Standard UDP Socket listeners.
Data Formats:
Input: .bst / .mat (Brainstorm native files). Intermediary: Binary .bin (Fixed-point Q15.16 format for the DE1-SoC). -
Communication & Protocols
Internal Bus (SoC):
AXI-Lightweight Bridge: For Control Signals (HPS → FPGA: "Start", "Stop", "Threshold"). AXI-H2F Bridge: For high-throughput Data Streaming (HPS → FPGA FIFO).External Network:
UDP/IP: For low-latency streaming of the 68-element source vector from the Board to the PC. SSH: For deploying code and debugging the Linux application. -
Development & Debugging Tools
Version Control: Git (GitHub).
Hardware Debugger: SignalTap II Logic Analyzer (Part of Quartus) – Essential for seeing what is happening inside the FPGA wires while it runs.
Network Analyzer: Wireshark or tcpdump – To verify packet structure and timing.
Command Line: Bash (for scripting the Linux build process on the DE1-SoC).
Onboarding documentation / Expectations
Onboarding instructions can be found in the repo CONTRIBUTING.md (to be created) in the wiki.
Expectations for team members depends on how much you want to commit. If you commit to contribute a lot of work then there will be big blocks of the project assigned to you.
What will participants learn?
Depending on which aspect of the project you work on, you will learn a variety of things. Here is a breakdown of what learning outcomes can be expected for each aspect of the project:
Learning Outcomes
Beginner:
How to interface a PC with an embedded system (Host-Target communication).
Basics of 3D medical data (vertices, faces, regions of interest).
How to write a UDP listener for real-time data visualization.
Intermediate:
The "SoC Flow": How an ARM processor talks to FPGA fabric (HPS-to-FPGA bridges).
Memory mapping: Controlling hardware registers from C code.
Fixed-point arithmetic: Converting float to int for hardware efficiency.
Advanced:
Designing a custom Matrix-Vector Multiplier (MVM) accelerator.
Optimizing memory bandwidth and handling FIFO streams.
End-to-end system latency analysis and optimization.
Data to use
We intend to use Open-Source EEG recording data, which will be TBD
Credit to collaborators
Project contributors are listed on the project README using [all-contributors github bot] (https://github.com/all-contributors/all-contributors).
Image
Type
visualization
Project Maturity Status
1 - basic structure
Topic
EEG_source_modelling
Tools
FieldTrip
Programming language
other
Modalities
EEG
Git skills
1_commit_push, 2_branches_PRs
Anything else?
No response
Things to do after the project is submitted and ready to review.
- Short summary of your project pitch to present during the hackathon.