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 1.2a - Added a protection for when the integer divider has less than 2 bits. 1.2b- Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters. 1.1 - Fixed a bug with some Modelsim versions where its 'Compile/Compile Options/Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'. 1.0 - Initial release.
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‎hdl/BHG_FP_clk_divider.v‎

Lines changed: 39 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,14 @@
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// ******************************************************************************************************
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//
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// BHG_FP_clk_divider.v V1.1, August 2022.
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// BHG_FP_clk_divider.v V1.2, August 2022.
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// Floating point clock divider/synthesizer.
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// 24.16 (m.n) bit floating point clock divider. (Actually it is a fixed point fractional divider.)
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//
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// 1.2 - Added a protection for when the integer divider has less than 2 bits.
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// - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
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// 1.1 - Fixed a bug with some Modelsim versions where its 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.
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// 1.0 - Initial release.
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//
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// Written by Brian Guralnick.
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// https://github.com/BrianHGinc / or / https://www.eevblog.com/forum/fpga/ User BrianHG.
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//
@@ -37,6 +42,37 @@ parameter INPUT_CLK_HZ = 100000000 ; // Source clk_in frequency in Hz.
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parameter OUTPUT_CLK_HZ = 3579545 ; // Desired clk_out frequency in Hz.
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// ****************************************************************************
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// Inoperable Parameter Error
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// ****************************************************************************
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generate
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if ( (OUTPUT_CLK_HZ*2)>INPUT_CLK_HZ ) initial begin
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$display("");
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$display(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$display(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXX BHG_FP_clk_divider.v inoperable parameter error. XXXXX");
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$display(" XXXXX https://github.com/BrianHGinc XXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$display(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXX BHG_FP_clk_divider.v can only generate an output clock at least 1/2 the source clock frequency. XXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXX Your current set parameters: XXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXX .INPUT_CLK_HZ = %d Hz. XXXXX",31'(INPUT_CLK_HZ));
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$display(" XXXXX .OUTPUT_CLK_HZ = %d Hz. XXXXX",31'(OUTPUT_CLK_HZ));
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$display(" XXXXX XXXXX");
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$display(" XXXXX .OUTPUT_CLK_HZ must be less than or equal to .INPUT_CLK_HZ/2 for BHG_FP_clk_divider.v to function. XXXXX");
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$display(" XXXXX XXXXX");
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$display(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$warning(" XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX");
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$error;
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$stop;
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end
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endgenerate
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// *************************************************************************************************************************************************************
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// Forcing 64 bits is required due to a ModelSim internal bug where if 'PLL1_OUT_TRUE_HZ*655360' exceeds 31 bits, it's considered negative and cropped
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// when computing the localparam. So, never use 'localparam int' when going above 2 billion anywhere inside, or you will get bogus results.
@@ -90,7 +126,8 @@ endgenerate
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// Floating point clock divider logic.
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// ****************************************************************************
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localparam mb = $clog2(clk_per_int);
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localparam pmb = $clog2(clk_per_int);
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localparam mb = (pmb<2) ? 2 : pmb ; // Protection for when the integer divider has less than 2 bits.
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reg [mb-1:0] clk_cnt_m = (mb)'(0) ; // This integer counts up 1 by 1 requiring manual bit reduction 'mb' for minimum logic cells.
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reg [16:0] clk_cnt_n = 17'd0 ; // This fractional int adds upward by a fixed parameter, the FPGA compiler is capable of automatically pruning unused bits.

‎hdl/BHG_FP_clk_divider_tb.v‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,13 @@
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// ***************************************************************************************************************
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// BHG_FP_clk_divider_tb.v V1.1, August 2022.
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// BHG_FP_clk_divider_tb.v V1.2, August 2022.
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// Floating point clock divider/synthesizer testbench.
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// 24.16 (m.n) bit floating point clock divider. (Actually it is a fixed point fractional divider.)
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//
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// 1.2 - Added a protection for when the integer divider has less than 2 bits.
7+
// - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
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// 1.1 - Fixed a bug with some Modelsim versions where its 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.
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// 1.0 - Initial release.
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//
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// Written by Brian Guralnick.
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// https://github.com/BrianHGinc / or / https://www.eevblog.com/forum/fpga/ User BrianHG.
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//

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