Update BHG_FP_clk_divider.v

Author: BrianHGinc

hdl/BHG_FP_clk_divider.v

@@ -4,6 +4,7 @@
 // Floating point clock divider/synthesizer.
 // 24.16 (m.n) bit floating point clock divider. (Actually it is a fixed point fractional divider.)
 //
+// 1.3 - Corrected the PPM calculation + added 1 bit to the M divider counter for the occasional requirement. (Thanks to 'dennowiggle' for catching the error)
 // 1.2 - Added a protection for when the integer divider has less than 2 bits.
 //     - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
 // 1.1 - Fixed a bug with some Modelsim versions where its 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.
@@ -87,7 +88,7 @@ localparam [15:0] clk_per_f        = USE_FLOATING_DIVIDE  ? clk_per_x65k[15:0]
 
 localparam [63:0] clk_tru_hzX100   = INPUT_CLK_HZ * 6553600 / (clk_per_int*65536+clk_per_f)            ; // Calculate the true output clock X 100.
 localparam signed clk_dif_hzX100   = (clk_tru_hzX100 - (OUTPUT_CLK_HZ*100))                            ;
-localparam signed clk_ppm_x100     =  clk_dif_hzX100 * OUTPUT_CLK_HZ / 1000000                         ; // Calculate the PPM offset error X 100.
+localparam signed clk_ppm_x100     =  clk_dif_hzX100 * 1000000 / OUTPUT_CLK_HZ                         ; // Calculate the PPM offset error X 100.
 localparam [63:0] clk_jitterx100   = (clk_per_f==0) ? 0 : (100000*1000000/INPUT_CLK_HZ) /2             ; // Calculate the occasional jitter X 100 generated by the floating point clock correction clock step.  
 
 localparam real   f_tru            = clk_tru_hzX100                                                    ; // Necessary for being able to display the decimal point
@@ -126,7 +127,7 @@ endgenerate
 // Floating point clock divider logic.
 // ****************************************************************************
 
-localparam pmb = $clog2(clk_per_int);
+localparam pmb = $clog2(clk_per_int) + 1;
 localparam mb  = (pmb<2) ? 2 : pmb  ; // Protection for when the integer divider has less than 2 bits.
 
 reg [mb-1:0] clk_cnt_m = (mb)'(0) ; // This integer counts up 1 by 1 requiring manual bit reduction 'mb' for minimum logic cells.