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jacobly0adriweb
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Everything is broken.
1 parent 0706b1e commit c0c7d89

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27 files changed

+2795
-435
lines changed

27 files changed

+2795
-435
lines changed

core/arm/CMSIS/Core/Include/core_cm0plus.h

Lines changed: 23 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,9 @@
112112

113113
#endif
114114

115+
#ifndef NO_VOLATILE_CONST_IO
115116
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
117+
#endif
116118

117119

118120
#ifdef __cplusplus
@@ -166,18 +168,27 @@
166168
\li to specify the access to peripheral variables.
167169
\li for automatic generation of peripheral register debug information.
168170
*/
169-
#ifdef __cplusplus
170-
#define __I volatile /*!< Defines 'read only' permissions */
171+
#ifndef NO_VOLATILE_CONST_IO
172+
#ifdef __cplusplus
173+
#define __I volatile /*!< Defines 'read only' permissions */
174+
#else
175+
#define __I volatile const /*!< Defines 'read only' permissions */
176+
#endif
177+
#define __O volatile /*!< Defines 'write only' permissions */
178+
#define __IO volatile /*!< Defines 'read / write' permissions */
179+
180+
/* following defines should be used for structure members */
181+
#define __IM volatile const /*! Defines 'read only' structure member permissions */
182+
#define __OM volatile /*! Defines 'write only' structure member permissions */
183+
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
171184
#else
172-
#define __I volatile const /*!< Defines 'read only' permissions */
185+
#define __I /*!< Defines 'read only' permissions */
186+
#define __O /*!< Defines 'write only' permissions */
187+
#define __IO /*!< Defines 'read / write' permissions */
188+
#define __IM /*!< Defines 'read only' structure member permissions */
189+
#define __OM /*!< Defines 'write only' structure member permissions */
190+
#define __IOM /*!< Defines 'read / write' structure member permissions */
173191
#endif
174-
#define __O volatile /*!< Defines 'write only' permissions */
175-
#define __IO volatile /*!< Defines 'read / write' permissions */
176-
177-
/* following defines should be used for structure members */
178-
#define __IM volatile const /*! Defines 'read only' structure member permissions */
179-
#define __OM volatile /*! Defines 'write only' structure member permissions */
180-
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
181192

182193
/*@} end of group Cortex-M0+ */
183194

@@ -732,6 +743,7 @@ typedef struct
732743
#define __NVIC_SetPriorityGrouping(X) (void)(X)
733744
#define __NVIC_GetPriorityGrouping() (0U)
734745

746+
#ifndef NO_VOLATILE_CONST_IO
735747
/**
736748
\brief Enable Interrupt
737749
\details Enables a device specific interrupt in the NVIC interrupt controller.
@@ -1070,7 +1082,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
10701082
#endif
10711083

10721084
/*@} end of CMSIS_Core_SysTickFunctions */
1073-
1085+
#endif
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10751087

10761088

core/arm/README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
[`CMSIS`](arm/CMSIS) and [`samd21a`](arm/samd21a) contain select files unzipped unmodified from [Atmel SAMD21 Series Device Support (1.3.395)](http://packs.download.atmel.com/#ATSAMD21E18A) and [CMSIS (Cortex Microcontroller Software Interface Standard) (5.4.0)](http://packs.download.atmel.com/#ARMCM0P) respectively.
1+
[`CMSIS`](arm/CMSIS) and [`samd21a`](arm/samd21a) contain select files unzipped from [Atmel SAMD21 Series Device Support (1.3.395)](http://packs.download.atmel.com/#ATSAMD21E18A) and [CMSIS (Cortex Microcontroller Software Interface Standard) (5.4.0)](http://packs.download.atmel.com/#ARMCM0P) respectively and slightly modified.

core/arm/arm.c

Lines changed: 161 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,161 @@
1+
#include "armstate.h"
2+
#include "../defines.h"
3+
#include "../os/os.h"
4+
5+
#include <assert.h>
6+
#include <errno.h>
7+
#include <stdio.h>
8+
#include <stdlib.h>
9+
#include <string.h>
10+
11+
static void reset(arm_t *arm, uint8_t rcause) {
12+
sync_wake(&arm->sync);
13+
arm_mem_reset(&arm->mem, rcause);
14+
arm_cpu_reset(arm);
15+
spsc_queue_clear(&arm->usart[0]);
16+
spsc_queue_clear(&arm->usart[1]);
17+
}
18+
19+
static int arm_thrd(void *context) {
20+
arm_t *arm = context;
21+
reset(arm, PM_RCAUSE_POR);
22+
while (sync_loop(&arm->sync)) {
23+
uint8_t i = 0;
24+
spsc_queue_entry_t peek;
25+
uint16_t val;
26+
do {
27+
arm_cpu_execute(arm);
28+
} while (++i);
29+
peek = spsc_queue_peek(&arm->usart[0]);
30+
if (unlikely(peek != SPSC_QUEUE_INVALID_ENTRY &&
31+
arm_mem_usart_recv(arm, 3, peek))) {
32+
spsc_queue_entry_t entry = spsc_queue_dequeue(&arm->usart[0]);
33+
(void)entry;
34+
assert(entry == peek && "Already successfully peeked");
35+
}
36+
if (unlikely(spsc_queue_flush(&arm->usart[1]) &&
37+
arm_mem_usart_send(arm, 3, &val))) {
38+
bool success = spsc_queue_enqueue(&arm->usart[0], val);
39+
(void)success;
40+
assert(success && "Already successfully flushed, so can't fail");
41+
}
42+
}
43+
spsc_queue_destroy(&arm->usart[1]);
44+
spsc_queue_destroy(&arm->usart[0]);
45+
arm_mem_destroy(&arm->mem);
46+
free(arm);
47+
return 0;
48+
}
49+
50+
arm_t *arm_create(void) {
51+
arm_t *arm = malloc(sizeof(arm_t));
52+
if (likely(arm)) {
53+
if (likely(sync_init(&arm->sync))) {
54+
if (likely(arm_mem_init(&arm->mem))) {
55+
if (likely(spsc_queue_init(&arm->usart[0]))) {
56+
if (likely(spsc_queue_init(&arm->usart[1]))) {
57+
arm->debug = false;
58+
if (likely(thrd_create(&arm->thrd, &arm_thrd, arm) == thrd_success)) {
59+
return arm;
60+
}
61+
spsc_queue_destroy(&arm->usart[1]);
62+
}
63+
spsc_queue_destroy(&arm->usart[0]);
64+
}
65+
arm_mem_destroy(&arm->mem);
66+
}
67+
sync_destroy(&arm->sync);
68+
}
69+
free(arm);
70+
}
71+
return NULL;
72+
}
73+
74+
void arm_destroy(arm_t *arm) {
75+
if (arm) {
76+
sync_enter(&arm->sync);
77+
arm->sync.run = false;
78+
thrd_detach(arm->thrd);
79+
sync_leave(&arm->sync);
80+
}
81+
}
82+
83+
void arm_reset(arm_t *arm) {
84+
sync_enter(&arm->sync);
85+
reset(arm, PM_RCAUSE_EXT);
86+
sync_leave(&arm->sync);
87+
}
88+
89+
bool arm_load(arm_t *arm, const char *path) {
90+
bool success = false;
91+
FILE *file = fopen_utf8(path, "rb");
92+
if (likely(file)) {
93+
sync_enter(&arm->sync);
94+
success = arm_mem_load_rom(&arm->mem, file);
95+
fclose(file);
96+
reset(arm, PM_RCAUSE_POR);
97+
//arm->debug = true;
98+
sync_leave(&arm->sync);
99+
}
100+
return success;
101+
}
102+
103+
void arm_spi_sel(arm_t *arm, bool low) {
104+
sync_enter(&arm->sync);
105+
sync_wake(&arm->sync);
106+
//printf("%c\n", low ? 'L' : 'H');
107+
arm_mem_spi_sel(arm, 0, low);
108+
sync_run_leave(&arm->sync);
109+
}
110+
111+
static void debug_byte(bool dir, unsigned char c) {
112+
//printf("\x1b[%dm%02X\x1b[m", 94 + dir, c);
113+
//fflush(stdout);
114+
}
115+
116+
static void debug_char(bool dir, char c) {
117+
if (c >= ' ' && c <= '~') {
118+
//printf("\x1b[%dm%c\x1b[m", 94 + dir, c);
119+
//fflush(stdout);
120+
}
121+
}
122+
123+
uint8_t arm_spi_peek(arm_t *arm, uint32_t *res) {
124+
sync_enter(&arm->sync);
125+
sync_wake(&arm->sync);
126+
uint8_t bits = arm_mem_spi_peek(arm, 0, res);
127+
if (bits == 8) {
128+
debug_byte(true, *res);
129+
}
130+
sync_run_leave(&arm->sync);
131+
return bits;
132+
}
133+
134+
uint8_t arm_spi_xfer(arm_t *arm, uint32_t val, uint32_t *res) {
135+
sync_enter(&arm->sync);
136+
sync_wake(&arm->sync);
137+
debug_byte(false, val);
138+
//printf("%02X ", val);
139+
arm_mem_spi_xfer(arm, 0, val);
140+
uint8_t bits = arm_mem_spi_peek(arm, 0, res);
141+
if (bits == 8) {
142+
debug_byte(true, *res);
143+
}
144+
//printf("<-> %02X\n", *res);
145+
sync_run_leave(&arm->sync);
146+
return bits;
147+
}
148+
149+
bool arm_usart_send(arm_t *arm, uint8_t val) {
150+
bool success = spsc_queue_enqueue(&arm->usart[0], val);
151+
if (likely(success)) {
152+
(void)spsc_queue_flush(&arm->usart[0]);
153+
}
154+
return success;
155+
}
156+
157+
bool arm_usart_recv(arm_t *arm, uint8_t *val) {
158+
spsc_queue_entry_t entry = spsc_queue_dequeue(&arm->usart[1]);
159+
*val = entry;
160+
return entry != SPSC_QUEUE_INVALID_ENTRY;
161+
}

core/arm/arm.h

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
#ifndef ARM_H
2+
#define ARM_H
3+
4+
#include <stdbool.h>
5+
#include <stdint.h>
6+
7+
typedef struct arm arm_t;
8+
9+
#ifdef __cplusplus
10+
extern "C" {
11+
#endif
12+
13+
arm_t *arm_create(void);
14+
void arm_destroy(arm_t *arm);
15+
16+
/* Thread-safe */
17+
void arm_reset(arm_t *arm);
18+
bool arm_load(arm_t *arm, const char *path);
19+
void arm_spi_sel(arm_t *arm, bool low);
20+
uint8_t arm_spi_peek(arm_t *arm, uint32_t *res);
21+
uint8_t arm_spi_xfer(arm_t *arm, uint32_t val, uint32_t *res);
22+
bool arm_usart_send(arm_t *arm, uint8_t val);
23+
bool arm_usart_recv(arm_t *arm, uint8_t *val);
24+
25+
#ifdef __cplusplus
26+
}
27+
#endif
28+
29+
#endif

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