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jrtc27resistor
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[ELF][RISCV] Stop using CSub for capability subtraction
This code is currently dead since we emit an all-zeroes PLT header on CHERI-RISC-V, but will soon be used. Fixes: 05652b9 ("[CHERI-RISC-V] Remove CSub")
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lld/ELF/Arch/RISCV.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ enum Op {
7878
CIncOffsetImm = 0x105b,
7979
CLC_64 = 0x3003,
8080
CLC_128 = 0x200f,
81-
CSub = 0x2800005b,
8281

8382
AUIPCC = 0x17,
8483
AUICGP = 0x7b,
@@ -272,12 +271,12 @@ void RISCV::writePltHeader(uint8_t *buf) const {
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// (c)sub t1, (c)t1, (c)t3
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// l[wdc] (c)t3, %pcrel_lo(1b)((c)t2); (c)t3 = _dl_runtime_resolve
274273
// addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
275-
// addi t0, t2, %pcrel_lo(1b)
276-
// srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
277-
// l[wd] t0, Wordsize(t0); t0 = link_map
278-
// jr t3
279-
uint32_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
280-
uint32_t ptrsub = ctx.arg.isCheriAbi ? CSub : SUB;
274+
// addi/cincoffset (c)t0, (c)t2, %pcrel_lo(1b)
275+
// (if shift != 0): srli t1, t1, shift; t1 = &.got.plt[i] - &.got.plt[0]
276+
// l[wdc] (c)t0, Ptrsize((c)t0); (c)t0 = link_map
277+
// (c)jr (c)t3
278+
// (if shift == 0): nop
279+
uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
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uint32_t ptrload = ctx.arg.isCheriAbi ? ctx.arg.is64 ? CLC_128 : CLC_64
282281
: ctx.arg.is64 ? LD
283282
: LW;
@@ -287,7 +286,7 @@ void RISCV::writePltHeader(uint8_t *buf) const {
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uint32_t ptrsize =
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ctx.arg.isCheriAbi ? ctx.arg.capabilitySize : ctx.arg.wordsize;
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write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
290-
write32le(buf + 4, rtype(ptrsub, X_T1, X_T1, X_T3));
289+
write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
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write32le(buf + 8, itype(ptrload, X_T3, X_T2, lo12(offset)));
292291
write32le(buf + 12, itype(ADDI, X_T1, X_T1, -ctx.target->pltHeaderSize - 12));
293292
write32le(buf + 16, itype(ptraddi, X_T0, X_T2, lo12(offset)));

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