[CHERIoT] Create an XCheriot1 processor feature.

Author: resistor

clang/test/Driver/print-supported-extensions-riscv.c

@@ -151,6 +151,7 @@
 // CHECK-NEXT:     svpbmt               1.0       'Svpbmt' (Page-Based Memory Types)
 // CHECK-NEXT:     svvptc               1.0       'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
 // CHECK-NEXT:     xcheri               0.0       'XCheri' (Implements CHERI extension)
+// CHECK-NEXT:     xcheriot1            1.0       'XCheriot1' (Implements Cheriot1 extension)
 // CHECK-NEXT:     xcvalu               1.0       'XCValu' (CORE-V ALU Operations)
 // CHECK-NEXT:     xcvbi                1.0       'XCVbi' (CORE-V Immediate Branching)
 // CHECK-NEXT:     xcvbitmanip          1.0       'XCVbitmanip' (CORE-V Bit Manipulation)

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -145,6 +145,12 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (FeatureBits[RISCV::Feature32Bit] &&
       FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV32 and RV64 can't be combined");
+  if (FeatureBits[RISCV::FeatureVendorXCheriot1]) {
+    if (!FeatureBits[RISCV::FeatureVendorXCheri])
+      report_fatal_error("XCheriotV1 extension requires XCheri extension");
+    if (!FeatureBits[RISCV::FeatureCapMode])
+      report_fatal_error("XCheriotV1 extension requires CapMode");
+  }
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1397,6 +1397,9 @@ def IsPureCapABI
 def NotPureCapABI
     : Predicate<"!RISCVABI::isCheriPureCapABI(Subtarget->getTargetABI())">;
 
+def FeatureVendorXCheriot1
+    : RISCVExtension<1, 0, "Implements Cheriot1 extension">;
+
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -597,12 +597,8 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
                                           FeatureStdExtZcmp]>;
 
 // NB: FeatureCheri =>'s RVC (!FeatureCheriNoRVC)
-def CHERIOT : RISCVProcessorModel<"cheriot",
-                                   NoSchedModel,
-                                   [Feature32Bit,
-                                    FeatureVendorXCheri,
-                                    FeatureCapMode,
-                                    FeatureStdExtC,
-                                    FeatureStdExtE,
-                                    FeatureStdExtM,
-                                    FeatureUnalignedScalarMem]>;
+def CHERIOT : RISCVProcessorModel<"cheriot", NoSchedModel,
+                                  [Feature32Bit, FeatureVendorXCheri,
+                                   FeatureVendorXCheriot1, FeatureCapMode,
+                                   FeatureStdExtC, FeatureStdExtE,
+                                   FeatureStdExtM, FeatureUnalignedScalarMem]>;

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

@@ -1077,6 +1077,7 @@ R"(All available -march extensions for RISC-V
     svpbmt               1.0
     svvptc               1.0
     xcheri               0.0
+    xcheriot1            1.0
     xcvalu               1.0
     xcvbi                1.0
     xcvbitmanip          1.0