[CHERIoT] Minor test fix needed to make the test pass on cheriot-upstream

resistor · resistor · commit 3af1e4ab217d · 2025-06-01T13:51:40.000+10:00
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+cap-mode < %s | FileCheck %s
+; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+c,+xcheriot,+xcheri,+cap-mode < %s | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200"
 target triple = "riscv32cheriot-unknown-cheriotrtos"

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+cap-mode < %s \| FileCheck %s`
	`1`	`+; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+c,+xcheriot,+xcheri,+cap-mode < %s \| FileCheck %s`
`2`	`2`
`3`	`3`	`target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200"`
`4`	`4`	`target triple = "riscv32cheriot-unknown-cheriotrtos"`