[CHERIOT] Add a TTI callback to disallow LSR base register expressions.

This allows us to turn on SCEV for cheriot, with the caveat that we need
to disallow LSR base register expressions that are negatively indexed, since
they may not be representable on cheriot.

Author: resistor

llvm/include/llvm/Analysis/TargetTransformInfo.h

@@ -787,6 +787,8 @@ class TargetTransformInfo {
   AddressingModeKind getPreferredAddressingMode(const Loop *L,
                                                 ScalarEvolution *SE) const;
 
+  bool isLegalBaseRegForLSR(const SCEV *) const;
+
   /// Return true if the target supports masked store.
   bool isLegalMaskedStore(Type *DataType, Align Alignment) const;
   /// Return true if the target supports masked load.
@@ -1996,6 +1998,7 @@ class TargetTransformInfo::Concept {
                           TargetLibraryInfo *LibInfo) = 0;
   virtual AddressingModeKind
     getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const = 0;
+  virtual bool isLegalBaseRegForLSR(const SCEV *) const = 0;
   virtual bool isLegalMaskedStore(Type *DataType, Align Alignment) = 0;
   virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment) = 0;
   virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
@@ -2534,6 +2537,9 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
                                ScalarEvolution *SE) const override {
     return Impl.getPreferredAddressingMode(L, SE);
   }
+  bool isLegalBaseRegForLSR(const SCEV *S) const override {
+    return Impl.isLegalBaseRegForLSR(S);
+  }
   bool isLegalMaskedStore(Type *DataType, Align Alignment) override {
     return Impl.isLegalMaskedStore(DataType, Alignment);
   }

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

@@ -276,6 +276,8 @@ class TargetTransformInfoImplBase {
     return TTI::AMK_None;
   }
 
+  bool isLegalBaseRegForLSR(const SCEV *S) const { return true; }
+
   bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
     return false;
   }

llvm/lib/Analysis/ScalarEvolution.cpp

@@ -6296,12 +6296,6 @@ const SCEV *ScalarEvolution::createNodeForGEP(GEPOperator *GEP) {
   assert(GEP->getSourceElementType()->isSized() &&
          "GEP source element type must be sized");
 
-  const DataLayout &DL = F.getParent()->getDataLayout();
-  // FIXME: Ideally, we should teach Scalar Evolution to
-  // understand fat pointers.
-  if (DL.isFatPointer(GEP->getPointerOperandType()->getPointerAddressSpace()))
-    return getUnknown(GEP);
-
   SmallVector<const SCEV *, 4> IndexExprs;
   for (Value *Index : GEP->indices())
     IndexExprs.push_back(getSCEV(Index));

llvm/lib/Analysis/TargetTransformInfo.cpp

@@ -463,6 +463,10 @@ TargetTransformInfo::getPreferredAddressingMode(const Loop *L,
   return TTIImpl->getPreferredAddressingMode(L, SE);
 }
 
+bool TargetTransformInfo::isLegalBaseRegForLSR(const SCEV *S) const {
+  return TTIImpl->isLegalBaseRegForLSR(S);
+}
+
 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
                                              Align Alignment) const {
   return TTIImpl->isLegalMaskedStore(DataType, Alignment);

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -9,6 +9,7 @@
 #include "RISCVTargetTransformInfo.h"
 #include "MCTargetDesc/RISCVMatInt.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/BasicTTIImpl.h"
 #include "llvm/CodeGen/CostTable.h"
@@ -2401,6 +2402,26 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
   return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
 }
 
+bool RISCVTTIImpl::isLegalBaseRegForLSR(const SCEV *S) const {
+  if (ST->hasVendorXCheriot()) {
+    // Disallow any add-recurrence SCEV where the base offset is negative.
+    // This is needed because CHERIoT can't represent pointers before the
+    // beginning of an array.
+    if (const auto *AddRec = dyn_cast<SCEVAddRecExpr>(S)) {
+      const auto *StartAdd = dyn_cast<SCEVAddExpr>(AddRec->getStart());
+      if (StartAdd) {
+        const auto *Offset = dyn_cast<SCEVConstant>(StartAdd->getOperand(0));
+        if (Offset && Offset->getValue()->isNegative())
+          return false;
+        Offset = dyn_cast<SCEVConstant>(StartAdd->getOperand(1));
+        if (Offset && Offset->getValue()->isNegative())
+          return false;
+      }
+    }
+  }
+  return BasicTTIImplBase::isLegalBaseRegForLSR(S);
+}
+
 bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                                  const TargetTransformInfo::LSRCost &C2) {
   // RISC-V specific here are "instruction number 1st priority".

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -394,6 +394,8 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
   TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L,
                                                      ScalarEvolution *SE) const;
 
+  bool isLegalBaseRegForLSR(const SCEV *S) const;
+
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
     if (Vector)
       return RISCVRegisterClass::VRRC;

llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp

@@ -1516,6 +1516,10 @@ void Cost::RateFormula(const Formula &F,
       return;
   }
   for (const SCEV *BaseReg : F.BaseRegs) {
+    if (!TTI->isLegalBaseRegForLSR(BaseReg)) {
+      Lose();
+      return;
+    }
     if (VisitedRegs.count(BaseReg)) {
       Lose();
       return;