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[CHERIoT] Add support for a few missing f64-in-cap-register operations.
We previously would error on: - Extensions from f32 to f64, complicated by f32 being illegal but f64 legal. - Selects where the values are f64, but the comparison is on integers.
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6 files changed

+127
-25
lines changed

6 files changed

+127
-25
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1145,6 +1145,10 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
11451145
case ISD::STRICT_FP_TO_BF16:
11461146
case ISD::STRICT_FP_ROUND:
11471147
case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
1148+
case ISD::STRICT_FP_EXTEND:
1149+
case ISD::FP_EXTEND:
1150+
Res = SoftenFloatOp_FP_EXTEND(N);
1151+
break;
11481152
case ISD::STRICT_FP_TO_SINT:
11491153
case ISD::STRICT_FP_TO_UINT:
11501154
case ISD::FP_TO_SINT:
@@ -1234,6 +1238,33 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
12341238
return Tmp.first;
12351239
}
12361240

1241+
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(SDNode *N) {
1242+
assert(N->getOpcode() == ISD::FP_EXTEND ||
1243+
N->getOpcode() == ISD::STRICT_FP_EXTEND);
1244+
1245+
bool IsStrict = N->isStrictFPOpcode();
1246+
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
1247+
EVT SVT = Op.getValueType();
1248+
EVT RVT = N->getValueType(0);
1249+
EVT FloatRVT = RVT;
1250+
1251+
RTLIB::Libcall LC = RTLIB::getFPEXT(SVT, FloatRVT);
1252+
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
1253+
1254+
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1255+
Op = GetSoftenedFloat(Op);
1256+
TargetLowering::MakeLibCallOptions CallOptions;
1257+
CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
1258+
std::pair<SDValue, SDValue> Tmp =
1259+
TLI.makeLibCall(DAG, LC, RVT, Op, CallOptions, SDLoc(N), Chain);
1260+
if (IsStrict) {
1261+
ReplaceValueWith(SDValue(N, 1), Tmp.second);
1262+
ReplaceValueWith(SDValue(N, 0), Tmp.first);
1263+
return SDValue();
1264+
}
1265+
return Tmp.first;
1266+
}
1267+
12371268
SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
12381269
SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
12391270
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -642,6 +642,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
642642
SDValue SoftenFloatOp_BITCAST(SDNode *N);
643643
SDValue SoftenFloatOp_BR_CC(SDNode *N);
644644
SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
645+
SDValue SoftenFloatOp_FP_EXTEND(SDNode *N);
645646
SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
646647
SDValue SoftenFloatOp_FP_TO_XINT_SAT(SDNode *N);
647648
SDValue SoftenFloatOp_LROUND(SDNode *N);

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -739,6 +739,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
739739
setOperationAction({ISD::SELECT_CC, ISD::SETCC}, MVT::i32, Custom);
740740
setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, MVT::i32, LibCall);
741741
setOperationAction({ISD::UINT_TO_FP, ISD::SINT_TO_FP}, MVT::i32, LibCall);
742+
setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f32,
743+
Custom);
742744

743745
static const unsigned CheriotF64ExpandOps[] = {
744746
ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
@@ -748,7 +750,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
748750
ISD::SETCC, ISD::FMAXIMUM, ISD::FMINIMUM, ISD::STRICT_FADD,
749751
ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
750752
ISD::STRICT_FMA, ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
751-
ISD::BR_CC};
753+
ISD::BR_CC, ISD::SELECT};
752754
setOperationAction(CheriotF64ExpandOps, MVT::f64, Expand);
753755
setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
754756
}
@@ -6768,7 +6770,8 @@ RISCVTargetLowering::lowerConstantFP(SDValue Op, SelectionDAG &DAG,
67686770

67696771
// Materialize 0.0 as cnull
67706772
if (Val == 0)
6771-
return DAG.getRegister(getNullCapabilityRegister(), MVT::f64);
6773+
return DAG.getCopyFromReg(DAG.getEntryNode(), DL,
6774+
getNullCapabilityRegister(), VT);
67726775

67736776
// Otherwise, materialize the low part into a 32-bit register.
67746777
auto Lo = DAG.getConstant(Val & 0xFFFFFFFF, DL, MVT::i32);
@@ -9501,8 +9504,8 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
95019504
// Perform SELECT_CC on f64 by bitcasting through c64.
95029505
SDValue LHSCap = DAG.getBitcast(MVT::c64, TrueV);
95039506
SDValue RHSCap = DAG.getBitcast(MVT::c64, FalseV);
9504-
SDValue Select =
9505-
DAG.getNode(ISD::SELECT, DL, MVT::c64, CondV, LHSCap, RHSCap);
9507+
SDValue Select = lowerSELECT(
9508+
DAG.getNode(ISD::SELECT, DL, MVT::c64, CondV, LHSCap, RHSCap), DAG);
95069509
return DAG.getBitcast(MVT::f64, Select);
95079510
}
95089511

@@ -22583,6 +22586,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2258322586
case RISCV::Select_GPR_Using_CC_UImmLog2XLen_NDS:
2258422587
case RISCV::Select_GPR_Using_CC_UImm7_NDS:
2258522588
case RISCV::Select_GPCR_Using_CC_GPR:
22589+
case RISCV::Select_GPCR_f64_Using_CC_GPR:
2258622590
case RISCV::Select_FPR16_Using_CC_GPR:
2258722591
case RISCV::Select_FPR16INX_Using_CC_GPR:
2258822592
case RISCV::Select_FPR32_Using_CC_GPR:

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1559,6 +1559,7 @@ def : CheriSetCCPatGpcrGpcr<setge, (XORI (SLT node:$rs1, node:$rs2), 1)>;
15591559
def : CheriSetCCPatGpcrGpcr<setle, (XORI (SLT node:$rs2, node:$rs1), 1)>;
15601560

15611561
defm Select_GPCR : SelectCC_GPR_rrirr<GPCR, CLenVT>;
1562+
defm Select_GPCR_f64 : SelectCC_GPR_rrirr<GPCR, f64>;
15621563

15631564
/// Control-Flow Instructions
15641565

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -45,26 +45,20 @@ def isZEXT_B
4545
]>>>;
4646

4747
def isSelectPseudo
48-
: TIIPredicate<"isSelectPseudo",
49-
MCReturnStatement<
50-
CheckOpcode<[
51-
Select_GPR_Using_CC_GPR,
52-
Select_GPCR_Using_CC_GPR,
53-
Select_GPR_Using_CC_SImm5_CV,
54-
Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
55-
Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
56-
Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
57-
Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
58-
Select_GPR_Using_CC_UImmLog2XLen_NDS,
59-
Select_GPR_Using_CC_UImm7_NDS,
60-
Select_FPR16_Using_CC_GPR,
61-
Select_FPR16INX_Using_CC_GPR,
62-
Select_FPR32_Using_CC_GPR,
63-
Select_FPR32INX_Using_CC_GPR,
64-
Select_FPR64_Using_CC_GPR,
65-
Select_FPR64INX_Using_CC_GPR,
66-
Select_FPR64IN32X_Using_CC_GPR
67-
]>>>;
48+
: TIIPredicate<
49+
"isSelectPseudo",
50+
MCReturnStatement<CheckOpcode<
51+
[Select_GPR_Using_CC_GPR, Select_GPCR_Using_CC_GPR,
52+
Select_GPCR_f64_Using_CC_GPR, Select_GPR_Using_CC_SImm5_CV,
53+
Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
54+
Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
55+
Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
56+
Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
57+
Select_GPR_Using_CC_UImmLog2XLen_NDS,
58+
Select_GPR_Using_CC_UImm7_NDS, Select_FPR16_Using_CC_GPR,
59+
Select_FPR16INX_Using_CC_GPR, Select_FPR32_Using_CC_GPR,
60+
Select_FPR32INX_Using_CC_GPR, Select_FPR64_Using_CC_GPR,
61+
Select_FPR64INX_Using_CC_GPR, Select_FPR64IN32X_Using_CC_GPR]>>>;
6862

6963
// Returns true if this is a vector configuration instruction.
7064
def isVectorConfigInstr

‎llvm/test/CodeGen/RISCV/cheri/cheriot-f64-abi.ll‎

Lines changed: 72 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -o - %s --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+xcheriot,+xcheripurecap | FileCheck %s
2+
; RUN: llc -o - %s -mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+xcheriot,+xcheripurecap | FileCheck %s
33

44
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200"
55
target triple = "riscv32cheriot-unknown-cheriotrtos"
@@ -290,6 +290,77 @@ entry:
290290
ret double %b
291291
}
292292

293+
; Function Attrs: nounwind uwtable
294+
define dso_local noundef double @float2double(float noundef %x) local_unnamed_addr addrspace(200) #0 {
295+
; CHECK-LABEL: float2double:
296+
; CHECK: # %bb.0: # %start
297+
; CHECK-NEXT: ct.cincoffset csp, csp, -16
298+
; CHECK-NEXT: ct.csc cra, 8(csp) # 8-byte Folded Spill
299+
; CHECK-NEXT: .LBB16_1: # %start
300+
; CHECK-NEXT: # Label of block must be emitted
301+
; CHECK-NEXT: ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
302+
; CHECK-NEXT: ct.clc ct2, %cheriot_compartment_lo_i(.LBB16_1)(ct2)
303+
; CHECK-NEXT: ct.cjalr ct2
304+
; CHECK-NEXT: ct.clc cra, 8(csp) # 8-byte Folded Reload
305+
; CHECK-NEXT: ct.cincoffset csp, csp, 16
306+
; CHECK-NEXT: ct.cret
307+
start:
308+
%a = fpext float %x to double
309+
ret double %a
310+
}
311+
312+
define dso_local noundef float @double2float(double noundef %x) local_unnamed_addr addrspace(200) #0 {
313+
; CHECK-LABEL: double2float:
314+
; CHECK: # %bb.0: # %start
315+
; CHECK-NEXT: ct.cincoffset csp, csp, -16
316+
; CHECK-NEXT: ct.csc cra, 8(csp) # 8-byte Folded Spill
317+
; CHECK-NEXT: .LBB17_1: # %start
318+
; CHECK-NEXT: # Label of block must be emitted
319+
; CHECK-NEXT: ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
320+
; CHECK-NEXT: ct.clc ct2, %cheriot_compartment_lo_i(.LBB17_1)(ct2)
321+
; CHECK-NEXT: ct.cjalr ct2
322+
; CHECK-NEXT: ct.clc cra, 8(csp) # 8-byte Folded Reload
323+
; CHECK-NEXT: ct.cincoffset csp, csp, 16
324+
; CHECK-NEXT: ct.cret
325+
start:
326+
%a = fptrunc double %x to float
327+
ret float %a
328+
}
329+
330+
define dso_local noundef double @select_on_int(double noundef %x, double noundef %y, i64 noundef %z) local_unnamed_addr addrspace(200) #0 {
331+
; CHECK-LABEL: select_on_int:
332+
; CHECK: # %bb.0: # %start
333+
; CHECK-NEXT: ct.cincoffset csp, csp, -16
334+
; CHECK-NEXT: ct.csc cra, 8(csp) # 8-byte Folded Spill
335+
; CHECK-NEXT: ct.csc cs0, 0(csp) # 8-byte Folded Spill
336+
; CHECK-NEXT: slti s0, a3, 0
337+
; CHECK-NEXT: .LBB18_4: # %start
338+
; CHECK-NEXT: # Label of block must be emitted
339+
; CHECK-NEXT: ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___ltdf2)
340+
; CHECK-NEXT: ct.clc ct2, %cheriot_compartment_lo_i(.LBB18_4)(ct2)
341+
; CHECK-NEXT: ct.cjalr ct2
342+
; CHECK-NEXT: slti a0, a0, 0
343+
; CHECK-NEXT: bne s0, a0, .LBB18_2
344+
; CHECK-NEXT: # %bb.1: # %start
345+
; CHECK-NEXT: ct.cmove ca0, cnull
346+
; CHECK-NEXT: j .LBB18_3
347+
; CHECK-NEXT: .LBB18_2:
348+
; CHECK-NEXT: lui a0, 261888
349+
; CHECK-NEXT: ct.csethigh ca0, cnull, a0
350+
; CHECK-NEXT: .LBB18_3: # %start
351+
; CHECK-NEXT: ct.clc cra, 8(csp) # 8-byte Folded Reload
352+
; CHECK-NEXT: ct.clc cs0, 0(csp) # 8-byte Folded Reload
353+
; CHECK-NEXT: ct.cincoffset csp, csp, 16
354+
; CHECK-NEXT: ct.cret
355+
start:
356+
%a = icmp slt i64 %z, 0
357+
%b = fcmp olt double %x, %y
358+
%0 = xor i1 %a, %b
359+
%c = select i1 %0, double 1.0, double 0.0
360+
ret double %c
361+
}
362+
363+
293364
attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "cheri-compartment"="qoi_decode" "no-builtin-longjmp" "no-builtin-printf" "no-builtin-setjmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+e,+m,+relax,+unaligned-scalar-mem,+xcheri,+xcheriot,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheri-norvc,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
294365
attributes #1 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) "cheri-compartment"="qoi_decode" "no-builtin-longjmp" "no-builtin-printf" "no-builtin-setjmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+e,+m,+relax,+unaligned-scalar-mem,+xcheri,+xcheriot,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheri-norvc,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
295366
attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write) "cheri-compartment"="qoi_decode" "no-builtin-longjmp" "no-builtin-printf" "no-builtin-setjmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+e,+m,+relax,+unaligned-scalar-mem,+xcheri,+xcheriot,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheri-norvc,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

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