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jrtc27resistor
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[clang][CodeGen] Fix getSizeOfUnwindException for purecap
The exception_cleanup and private_1/private_2 members are all capabilities in purecap ABIs rather than uint64_t (or uint32_t followed by padding in the case of 32-bit) and so the size of the struct is larger. On a hypothetical 128-bit architecture they would also be 128-bit integers, so generalise this code to just look at the pointer size rather than be CHERI-specific. Fixes: CTSRD-CHERI#680
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clang/lib/CodeGen/TargetInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,8 @@ unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
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// PowerPC Linux
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// ARM Darwin (*not* EABI)
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// AArch64 Linux
86-
return 32;
86+
unsigned PointerSize = Info->getTarget().getPointerWidth(LangAS::Default) / 8;
87+
return PointerSize > 8 ? 4 * PointerSize : 32;
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}
8889

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bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,

clang/lib/CodeGen/Targets/Mips.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@ class MIPSTargetCodeGenInfo : public CommonCheriTargetCodeGenInfo {
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MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32, CodeGenModule &CGM)
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: CommonCheriTargetCodeGenInfo(
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std::make_unique<MipsABIInfo>(CGT, IsO32, CGM)),
58-
SizeOfUnwindException(IsO32 ? 24 : 32) {}
58+
SizeOfUnwindException(
59+
IsO32 ? 24 : TargetCodeGenInfo::getSizeOfUnwindException()) {}
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
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return 29;

clang/test/CodeGenCXX/cheri/size-of-unwind-exception.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
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// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
88

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/// Check that we use the correct size for struct _Unwind_Exception
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/// TODO: 64-bit CHERI architectures use the wrong size
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void foo();
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void bar(int *&);
@@ -31,7 +30,7 @@ void bar(int *&);
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// CHECK-MIPS-NEXT: br i1 [[MATCHES]], label [[CATCH:%.*]], label [[EH_RESUME:%.*]]
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// CHECK-MIPS: catch:
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// CHECK-MIPS-NEXT: [[TMP4:%.*]] = call ptr addrspace(200) @__cxa_begin_catch(ptr addrspace(200) [[TMP1]]) #[[ATTR3]]
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// CHECK-MIPS-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(200) [[TMP1]], i32 32
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// CHECK-MIPS-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(200) [[TMP1]], i32 64
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// CHECK-MIPS-NEXT: invoke void @_Z3barRPi(ptr addrspace(200) noundef nonnull align 16 dereferenceable(16) [[TMP5]])
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// CHECK-MIPS-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD1:%.*]]
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// CHECK-MIPS: invoke.cont2:
@@ -113,7 +112,7 @@ void bar(int *&);
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// CHECK-RV64-NEXT: br i1 [[MATCHES]], label [[CATCH:%.*]], label [[EH_RESUME:%.*]]
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// CHECK-RV64: catch:
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = call ptr addrspace(200) @__cxa_begin_catch(ptr addrspace(200) [[TMP1]]) #[[ATTR3]]
116-
// CHECK-RV64-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(200) [[TMP1]], i32 32
115+
// CHECK-RV64-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(200) [[TMP1]], i32 64
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// CHECK-RV64-NEXT: invoke void @_Z3barRPi(ptr addrspace(200) noundef nonnull align 16 dereferenceable(16) [[TMP5]])
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// CHECK-RV64-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD1:%.*]]
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// CHECK-RV64: invoke.cont2:

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