@@ -27,7 +27,8 @@ using namespace llvm::opt;
2727// Returns false if an error is diagnosed.
2828static bool getArchFeatures (const Driver &D, StringRef Arch,
2929 std::vector<StringRef> &Features,
30- const ArgList &Args) {
30+ const ArgList &Args,
31+ std::unique_ptr<llvm::RISCVISAInfo> &ISAInfoOut) {
3132 bool EnableExperimentalExtensions =
3233 Args.hasArg (options::OPT_menable_experimental_extensions);
3334 auto ISAInfo =
@@ -48,6 +49,7 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
4849 if (EnableExperimentalExtensions)
4950 Features.push_back (Args.MakeArgString (" +experimental" ));
5051
52+ ISAInfoOut = std::move (*ISAInfo);
5153 return true ;
5254}
5355
@@ -92,8 +94,9 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
9294 const ArgList &Args,
9395 std::vector<StringRef> &Features) {
9496 std::string MArch = getRISCVArch (Args, Triple);
97+ std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
9598
96- if (!getArchFeatures (D, MArch, Features, Args))
99+ if (!getArchFeatures (D, MArch, Features, Args, ISAInfo ))
97100 return ;
98101
99102 bool CPUFastScalarUnaligned = false ;
@@ -210,14 +213,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
210213 // +xcheriot implies both +xcheri and +xcheripurecap
211214 Features.push_back (" +xcheriot" );
212215 } else if (IsPureCapability) {
213- auto ISAInfo = llvm::RISCVISAInfo::parseFeatures (
214- Triple.isArch32Bit () ? 32 : 64 ,
215- std::vector<std::string>(Features.begin (), Features.end ()));
216- if (!ISAInfo) {
217- handleAllErrors (ISAInfo.takeError (), [&](llvm::StringError &ErrMsg) {
218- D.Diag (diag::err_invalid_feature_combination) << ErrMsg.getMessage ();
219- });
220- } else if (!(*ISAInfo)->hasExtension (" xcheri" )) {
216+ if (!ISAInfo->hasExtension (" xcheri" )) {
221217 D.Diag (diag::err_riscv_invalid_abi)
222218 << A->getValue ()
223219 << " pure capability ABI requires xcheri extension to be specified" ;
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