[CHERIoT] Expand small atomics inline when XCheriot is enabled.

Author: resistor

clang/lib/Basic/Targets/RISCV.h

@@ -293,6 +293,9 @@ class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 
     if (ISAInfo->hasExtension("a"))
       MaxAtomicInlineWidth = 32;
+    else if (ISAInfo->hasExtension("xcheriot"))
+      // XCheriot implies atomic libcalls up to cap size.
+      MaxAtomicInlineWidth = 8;
   }
 
   uint64_t getPointerRangeForCHERICapability() const override { return 32; }

clang/test/CodeGen/cheri/riscv/cheriot-atomic-uintptr.c

@@ -7,22 +7,18 @@
 // CHECK-SAME: ) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
 // CHECK-NEXT:  [[ENTRY:.*]]:
 // CHECK-NEXT:    [[P:%.*]] = alloca ptr addrspace(200), align 8, addrspace(200)
-// CHECK-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca ptr addrspace(200), align 8, addrspace(200)
-// CHECK-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca ptr addrspace(200), align 8, addrspace(200)
-// CHECK-NEXT:    [[ATOMIC_TEMP2:%.*]] = alloca ptr addrspace(200), align 8, addrspace(200)
-// CHECK-NEXT:    call void @llvm.lifetime.start.p200(i64 8, ptr addrspace(200) nonnull [[P]]) #[[ATTR4:[0-9]+]]
-// CHECK-NEXT:    call cherilibcallcc void @__atomic_load(i32 noundef 8, ptr addrspace(200) noundef nonnull [[P]], ptr addrspace(200) noundef nonnull [[ATOMIC_TEMP]], i32 noundef 5) #[[ATTR5:[0-9]+]]
+// CHECK-NEXT:    call void @llvm.lifetime.start.p200(i64 8, ptr addrspace(200) nonnull [[P]]) #[[ATTR2:[0-9]+]]
+// CHECK-NEXT:    [[ATOMIC_LOAD:%.*]] = load atomic ptr addrspace(200), ptr addrspace(200) [[P]] seq_cst, align 8, !tbaa [[TBAA7:![0-9]+]]
 // CHECK-NEXT:    br label %[[ATOMIC_OP:.*]]
 // CHECK:       [[ATOMIC_OP]]:
-// CHECK-NEXT:    [[DOTIN:%.*]] = phi ptr addrspace(200) [ [[ATOMIC_TEMP]], %[[ENTRY]] ], [ [[ATOMIC_TEMP1]], %[[ATOMIC_OP]] ]
-// CHECK-NEXT:    [[TMP0:%.*]] = load ptr addrspace(200), ptr addrspace(200) [[DOTIN]], align 8, !tbaa [[TBAA7:![0-9]+]]
+// CHECK-NEXT:    [[TMP0:%.*]] = phi ptr addrspace(200) [ [[ATOMIC_LOAD]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr addrspace(200) [[TMP0]], i32 1
-// CHECK-NEXT:    store ptr addrspace(200) [[TMP0]], ptr addrspace(200) [[ATOMIC_TEMP1]], align 8, !tbaa [[TBAA11:![0-9]+]]
-// CHECK-NEXT:    store ptr addrspace(200) [[TMP1]], ptr addrspace(200) [[ATOMIC_TEMP2]], align 8, !tbaa [[TBAA11]]
-// CHECK-NEXT:    [[CALL:%.*]] = call cherilibcallcc zeroext i1 @__atomic_compare_exchange(i32 noundef 8, ptr addrspace(200) noundef nonnull [[P]], ptr addrspace(200) noundef nonnull [[ATOMIC_TEMP1]], ptr addrspace(200) noundef nonnull [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5) #[[ATTR5]]
-// CHECK-NEXT:    br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// CHECK-NEXT:    [[TMP2:%.*]] = cmpxchg ptr addrspace(200) [[P]], ptr addrspace(200) [[TMP0]], ptr addrspace(200) [[TMP1]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP3]] = extractvalue { ptr addrspace(200), i1 } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { ptr addrspace(200), i1 } [[TMP2]], 1
+// CHECK-NEXT:    br i1 [[TMP4]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
 // CHECK:       [[ATOMIC_CONT]]:
-// CHECK-NEXT:    call void @llvm.lifetime.end.p200(i64 8, ptr addrspace(200) nonnull [[P]]) #[[ATTR4]]
+// CHECK-NEXT:    call void @llvm.lifetime.end.p200(i64 8, ptr addrspace(200) nonnull [[P]]) #[[ATTR2]]
 // CHECK-NEXT:    ret void
 //
 void test1() {
@@ -31,8 +27,6 @@ void test1() {
 }
 //.
 // CHECK: [[TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
-// CHECK: [[META8]] = !{!"unsigned __intcap", [[META9:![0-9]+]], i64 0}
-// CHECK: [[META9]] = !{!"omnipotent char", [[META10:![0-9]+]], i64 0}
-// CHECK: [[META10]] = !{!"Simple C/C++ TBAA"}
-// CHECK: [[TBAA11]] = !{[[META9]], [[META9]], i64 0}
+// CHECK: [[META8]] = !{!"omnipotent char", [[META9:![0-9]+]], i64 0}
+// CHECK: [[META9]] = !{!"Simple C/C++ TBAA"}
 //.