Skip to content

Commit 958238b

Browse files
resistorresistor
committed
[CHERI] Rename +cap-mode to +xcheripurecap
This makes it interoperate properly with the rest of the RISCV extension framework, and is necessary to be able to make xcheriot imply it.
1 parent 0e1c976 commit 958238b

File tree

154 files changed

+317
-315
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

154 files changed

+317
-315
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -379,7 +379,7 @@ bool RISCVTargetInfo::initFeatureMap(
379379

380380
if (getTriple().getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) {
381381
Features["xcheri"] = true;
382-
Features["cap-mode"] = true;
382+
Features["xcheripurecap"] = true;
383383
Features["c"] = true;
384384
Features["e"] = true;
385385
Features["m"] = true;

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
220220
<< "pure capability ABI requires xcheri extension to be specified";
221221
return;
222222
}
223-
Features.push_back("+cap-mode");
223+
Features.push_back("+xcheripurecap");
224224
}
225225
}
226226

@@ -232,7 +232,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
232232
<< "pure capability ABI requires xcheri extension to be specified";
233233
return;
234234
}
235-
Features.push_back("+cap-mode");
235+
Features.push_back("+xcheripurecap");
236236
}
237237
}
238238

@@ -244,7 +244,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
244244
<< "pure capability ABI requires xcheri extension to be specified";
245245
return;
246246
}
247-
Features.push_back("+cap-mode");
247+
Features.push_back("+xcheripurecap");
248248
}
249249
}
250250

@@ -256,7 +256,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
256256
<< "pure capability ABI requires xcheri extension to be specified";
257257
return;
258258
}
259-
Features.push_back("+cap-mode");
259+
Features.push_back("+xcheripurecap");
260260
}
261261
}
262262

‎clang/test/CodeGen/cheri/cheriot-struct-ret.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -810,6 +810,6 @@ __attribute__((cheri_compartment("example"))) void CheckOnePtr () {
810810
}
811811

812812

813-
// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
814-
// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
815-
// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
813+
// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
814+
// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
815+
// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }

‎clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,6 @@ void func() {
4242
// CHECK: declare void @doSomething2(ptr addrspace(200) noundef) local_unnamed_addr addrspace(200) #2
4343

4444
// CHECK: attributes #0 = { "cheriot_sealed_value" }
45-
// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
46-
// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
45+
// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
46+
// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
4747
// CHECK: attributes #3 = { minsize nounwind optsize }

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,7 @@
152152
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
153153
// CHECK-NEXT: xcheri 0.0 'XCheri' (Implements CHERI extension)
154154
// CHECK-NEXT: xcheriot 1.0 'XCheriot' (Implements XCheriot extension)
155+
// CHECK-NEXT: xcheripurecap 0.0 'XCheriPureCap' (Implements CHERI pure capability mode)
155156
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
156157
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
157158
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)

‎lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
# REQUIRES: riscv
2-
# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheriot -filetype=obj %s -o %t.o
2+
# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheripurecap,+xcheriot -filetype=obj %s -o %t.o
33
# RUN: ld.lld %t.o -o %t.exe
44
# RUN: llvm-objdump -d %t.exe | FileCheck %s
55

66
.attribute 4, 16
7-
.attribute 5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0"
7+
.attribute 5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0_xcheripurecap1p0"
88
.section .text,"ax",@progbits
99
.globl _start
1010
.p2align 1
@@ -43,8 +43,8 @@ _start: # @_Z5entryv
4343
near:
4444
.word 1
4545

46-
# CHECK: 00012010 <near>:
47-
# CHECK-NEXT: 12010: 01 00 00 00 00 00 00 00
46+
# CHECK: 00012020 <near>:
47+
# CHECK-NEXT: 12020: 01 00 00 00 00 00 00 00
4848

4949
.type mid,@object
5050
.p2align 12, 0x0

‎llvm/lib/Object/ELFObjectFile.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,7 @@ Expected<SubtargetFeatures> ELFObjectFileBase::getRISCVFeatures() const {
383383

384384
if (PlatformFlags & ELF::EF_RISCV_CAP_MODE) {
385385
Features.AddFeature("xcheri");
386-
Features.AddFeature("cap-mode");
386+
Features.AddFeature("xcheripurecap");
387387
}
388388

389389
RISCVAttributeParser Attributes;

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3427,7 +3427,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
34273427
"option requires 'xcheri' extension");
34283428

34293429
getTargetStreamer().emitDirectiveOptionCapMode();
3430-
setFeatureBits(RISCV::FeatureCapMode, "cap-mode");
3430+
setFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap");
34313431
return false;
34323432
}
34333433

@@ -3440,7 +3440,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
34403440
"option requires 'xcheri' extension");
34413441

34423442
getTargetStreamer().emitDirectiveOptionNoCapMode();
3443-
clearFeatureBits(RISCV::FeatureCapMode, "cap-mode");
3443+
clearFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap");
34443444
return false;
34453445
}
34463446

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -668,13 +668,13 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
668668

669669
uint32_t Insn = support::endian::read32le(Bytes.data());
670670

671-
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureCapMode) &&
671+
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap) &&
672672
!STI.hasFeature(RISCV::Feature64Bit),
673673
DecoderTableRISCV32CapModeOnly_32,
674674
"RISCV32CapModeOnly_32 table");
675675
TRY_TO_DECODE(!STI.hasFeature(RISCV::Feature64Bit),
676676
DecoderTableRISCV32Only_32, "RISCV32Only_32 table");
677-
TRY_TO_DECODE_FEATURE(RISCV::FeatureCapMode, DecoderTableCapModeOnly_32,
677+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCheriPureCap, DecoderTableCapModeOnly_32,
678678
"CapModeOnly_32 table");
679679
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
680680
!STI.hasFeature(RISCV::Feature64Bit),
@@ -795,10 +795,10 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
795795

796796
uint32_t Insn = support::endian::read16le(Bytes.data());
797797
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit) &&
798-
STI.hasFeature(RISCV::FeatureCapMode),
798+
STI.hasFeature(RISCV::FeatureVendorXCheriPureCap),
799799
DecoderTableRISCV32CapModeOnly_16,
800800
"RISCV32CapModeOnly_16");
801-
TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureCapMode),
801+
TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap),
802802
DecoderTableCapModeOnly_16, "CapModeOnly_16 table");
803803
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
804804
DecoderTableRISCV32Only_16,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -368,7 +368,7 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
368368
// Given a compressed control flow instruction this function returns
369369
// the expanded instruction.
370370
unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
371-
bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureCapMode];
371+
bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureVendorXCheriPureCap];
372372

373373
switch (Op) {
374374
default:

0 commit comments

Comments
 (0)