[CHERIoT] Create an XCheriotV1 processor feature.

Author: resistor

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -145,6 +145,12 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (FeatureBits[RISCV::Feature32Bit] &&
       FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV32 and RV64 can't be combined");
+  if (FeatureBits[RISCV::FeatureVendorXCheriotV1]) {
+    if (!FeatureBits[RISCV::FeatureVendorXCheri])
+      report_fatal_error("XCheriotV1 extension requires XCheri extension");
+    if (!FeatureBits[RISCV::FeatureCapMode])
+      report_fatal_error("XCheriotV1 extension requires CapMode");
+  }
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1397,6 +1397,8 @@ def IsPureCapABI
 def NotPureCapABI
     : Predicate<"!RISCVABI::isCheriPureCapABI(Subtarget->getTargetABI())">;
 
+def FeatureVendorXCheriotV1 : RISCVExtension<0, 0, "Implements XCheriotV1 extension">;
+
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -601,6 +601,7 @@ def CHERIOT : RISCVProcessorModel<"cheriot",
                                    NoSchedModel,
                                    [Feature32Bit,
                                     FeatureVendorXCheri,
+                                    FeatureVendorXCheriotV1,
                                     FeatureCapMode,
                                     FeatureStdExtC,
                                     FeatureStdExtE,

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

@@ -1077,6 +1077,7 @@ R"(All available -march extensions for RISC-V
     svpbmt               1.0
     svvptc               1.0
     xcheri               0.0
+    xcheriot             0.0
     xcvalu               1.0
     xcvbi                1.0
     xcvbitmanip          1.0