[CHERI] Use ABI to deduce purecap instead of default addrspace

Author: veselypeta

clang/lib/CodeGen/CodeGenAction.cpp

@@ -851,8 +851,7 @@ void BackendConsumer::DiagnosticHandlerImpl(const DiagnosticInfo &DI) {
     bool BadDebugInfo = false;
     FullSourceLoc Loc =
         getBestLocationFromDebugLoc(DICI, BadDebugInfo, Filename, Line, Column);
-    const auto &DL = DICI.getFunction().getParent()->getDataLayout();
-    bool IsPurecap = DL.isFatPointer(DL.getDefaultGlobalsAddressSpace());
+    bool IsPurecap = Context->getTargetInfo().areAllPointersCapabilities();
 
     Diags.Report(Loc, diag::warn_fe_backend_cheri_inefficient)
         << DICI.getMessage();

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -3562,6 +3562,7 @@ class LLVM_ABI TargetLoweringBase {
   Register getNullCapabilityRegister() const {
     return NullCapabilityRegister;
   }
+  bool isCheriPureCap() const { return IsCheriPureCap; }
 
   /// Does this target require the clearing of high-order bits in a register
   /// passed to the fp16 to fp conversion library function.
@@ -3982,6 +3983,9 @@ class LLVM_ABI TargetLoweringBase {
   /// Should be one of c64/c128/c256
   MVT CapType = MVT();
 
+  /// All pointers are capabilities.
+  bool IsCheriPureCap = false;
+
   /// Whether CHERI Capability loads/stores can be used with unaligned addresses
   /// This makes it possible to do a tag-preserving copy even if the alignment
   /// is not statically known to be at least capability aligned.

llvm/lib/CodeGen/AtomicExpandPass.cpp

@@ -2117,13 +2117,10 @@ bool AtomicExpandImpl::expandAtomicOpToLibcall(
   // adding the 20+ new entries to RuntimeLibcalls.def. We also suffix with
   // _c for capability pointer arguments in hybrid mode.
   std::string LibcallName = TLI->getLibcallName(RTLibType);
-  // We are compiling for CHERI purecap mode if the default globals address
-  // space is a capability type.
-  bool IsCheriPurecap = DL.isFatPointer(DL.getDefaultGlobalsAddressSpace());
   if (ValueOperandIsCap) {
     LibcallName += "_cap";
   }
-  if (PointerOperandIsCap && !IsCheriPurecap) {
+  if (PointerOperandIsCap && !TLI->isCheriPureCap()) {
     // Add a _c suffix if the function uses capability pointer operands in
     // hybrid mode.
     assert(StringRef(LibcallName).starts_with("__atomic"));

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -344,6 +344,7 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
     : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
   CapType = STI.typeForCapabilities();
   assert(cheriCapabilityType().isFatPointer());
+  IsCheriPureCap = ABI.IsCheriPureCap();
 
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...).

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -172,12 +172,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     addRegisterClass(CapType, &RISCV::YGPRRegClass);
   }
 
-  if (Subtarget.hasVendorXCheri()) {
-    CapType = Subtarget.typeForCapabilities();
-    NullCapabilityRegister = RISCV::X0_Y;
-    addRegisterClass(CapType, &RISCV::YGPRRegClass);
-  }
-
   if (Subtarget.hasVendorXCheriot()) {
     // Cheriot holds f64's in capability registers.
     addRegisterClass(MVT::f64, &RISCV::YGPRRegClass);