[RISCV] Use new %code(expr) for lowerCheriCodeReference

jrtc27 · resistor · commit a6338514d87e · 2025-11-13T21:29:53.000-08:00
diff --git a/lld/test/ELF/cheri/exception-table.ll b/lld/test/ELF/cheri/exception-table.ll
@@ -15,12 +15,12 @@
 ; MIPS-OBJ-RELOCS-NEXT:   R_MIPS_CHERI_CAPABILITY/R_MIPS_NONE/R_MIPS_NONE .L_Z9test_weakll$local 0x34
 ; MIPS-OBJ-RELOCS-NEXT: }
 ; RV64-OBJ-RELOCS:      Section ({{.+}}) .rela.gcc_except_table {
-; RV64-OBJ-RELOCS-NEXT:   0x20 R_RISCV_CHERI_CAPABILITY .L_Z4testll$local 0x5C
-; RV64-OBJ-RELOCS-NEXT:   0x40 R_RISCV_CHERI_CAPABILITY .L_Z4testll$local 0x48
-; RV64-OBJ-RELOCS-NEXT:   0x80 R_RISCV_CHERI_CAPABILITY .L_Z5test2ll$local 0x44
+; RV64-OBJ-RELOCS-NEXT:   0x20 R_RISCV_CHERI_CAPABILITY_CODE .L_Z4testll$local 0x5C
+; RV64-OBJ-RELOCS-NEXT:   0x40 R_RISCV_CHERI_CAPABILITY_CODE .L_Z4testll$local 0x48
+; RV64-OBJ-RELOCS-NEXT:   0x80 R_RISCV_CHERI_CAPABILITY_CODE .L_Z5test2ll$local 0x44
 ; RV64-OBJ-RELOCS-NEXT:   0xA4 R_RISCV_ADD32 .L_ZTIl.DW.stub 0x0
 ; RV64-OBJ-RELOCS-NEXT:   0xA4 R_RISCV_SUB32 .L0 0x0
-; RV64-OBJ-RELOCS-NEXT:   0xC0 R_RISCV_CHERI_CAPABILITY .L_Z9test_weakll$local 0x1C
+; RV64-OBJ-RELOCS-NEXT:   0xC0 R_RISCV_CHERI_CAPABILITY_CODE .L_Z9test_weakll$local 0x1C
 ; RV64-OBJ-RELOCS-NEXT: }
 
 ;; This should work with both -z text and -z notext
@@ -94,11 +94,11 @@
 ; RV64-RELOCS-OVERRIDE: [[#%.16x,TEST_WEAK_OVERRIDE_ADDR:]] 8 FUNC    GLOBAL   DEFAULT     9 _Z9test_weakll{{$}}
 
 ; RV64-RELOCS: CHERI __cap_relocs [
-; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_ADDR]] (.L_Z4testll$local+92) Length: 116 Perms: Function
-; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_ADDR]] (.L_Z4testll$local+72) Length: 116 Perms: Function
-; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST2_ADDR]] (.L_Z5test2ll$local+68) Length: 124 Perms: Function
+; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_ADDR]] (.L_Z4testll$local+92) Length: 116 Perms: Code
+; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_ADDR]] (.L_Z4testll$local+72) Length: 116 Perms: Code
+; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST2_ADDR]] (.L_Z5test2ll$local+68) Length: 124 Perms: Code
 ; Next one references the local symbol, and uses that length rather than the override:
-; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_WEAK_ADDR]] (.L_Z9test_weakll$local+28) Length: 52 Perms: Function
+; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,TEST_WEAK_ADDR]] (.L_Z9test_weakll$local+28) Length: 52 Perms: Code
 ; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,PLT0_ADDR:]] (<unknown symbol>+0) Length: 80 Perms: Code
 ; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,PLT0_ADDR]] (<unknown symbol>+0) Length: 80 Perms: Code
 ; RV64-RELOCS-NEXT:   0x003{{.+}} Base: 0x[[#%x,PLT0_ADDR]] (<unknown symbol>+0) Length: 80 Perms: Code
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -17,6 +17,7 @@
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/Casting.h"
diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
@@ -210,3 +210,14 @@ int RISCVELFTargetObjectFile::getCheriCapabilitySize(
   const RISCVTargetMachine &RTM = static_cast<const RISCVTargetMachine &>(TM);
   return RTM.IsRV64() ? 16 : 8;
 }
+
+const MCExpr *
+RISCVELFTargetObjectFile::lowerCheriCodeReference(const MCSymbol *Sym,
+                                                  const MCExpr *Addend) const {
+  const MCExpr *Expr = MCSymbolRefExpr::create(Sym, getContext());
+  if (Addend != nullptr)
+    Expr = MCBinaryExpr::createAdd(Expr, Addend, getContext());
+  Expr = MCSpecifierExpr::create(Expr, ELF::R_RISCV_CHERI_CAPABILITY_CODE,
+                                 getContext());
+  return Expr;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h
@@ -62,6 +62,9 @@ class RISCVELFTargetObjectFile : public TargetLoweringObjectFileELF {
                                      const TargetMachine &TM) const override;
 
   int getCheriCapabilitySize(const TargetMachine &TM) const override;
+
+  const MCExpr *lowerCheriCodeReference(const MCSymbol *Sym,
+                                        const MCExpr *Addend) const override;
 };
 
 } // end namespace llvm
diff --git a/llvm/test/CodeGen/CHERI-Generic/Inputs/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/Inputs/landingpad-non-preemptible.ll
@@ -75,7 +75,8 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
 ; Note: RISC-V uses DW_EH_PE_udata4, so the 0xc marker uses 4 bytes instead of 1
 ; CHECK-NEXT:  [[SMALL_CS_DIRECTIVE:(\.byte)|(\.word)]] 12     # (landing pad is a capability)
-; CHECK-NEXT:  .chericap .Llpad0                               #     jumps to .Llpad0
+@IF-MIPS@; CHECK-NEXT:  .chericap .Llpad0                               #     jumps to .Llpad0
+@IF-RISCV@; CHECK-NEXT:  .chericap  %code(.L_Z8do_catchv$local+(.Ltmp2-.Lfunc_begin0))   #     jumps to .Ltmp2
 ; CHECK-NEXT:  .byte 3                               #   On action: 2
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Lfunc_begin0           # >> Call Site 2 <<
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Lfunc_end0-.Ltmp1             #   Call between .Ltmp1 and .Lfunc_end0
@@ -104,7 +105,7 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 ; RELOCS-LABEL:  Section ({{.+}}) .rela.gcc_except_table {
 @IF-MIPS@; RELOCS-NEXT:    0x10 R_MIPS_CHERI_CAPABILITY/R_MIPS_NONE/R_MIPS_NONE .Llpad0 0x0{{$}}
 @IF-MIPS@; RELOCS-NEXT:    R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE .L_ZTIi.DW.stub 0x0
-@IF-RISCV@; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY  .Llpad0 0x0{{$}}
+@IF-RISCV@; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY_CODE .Llpad0 0x0{{$}}
 @IF-RISCV@; RELOCS-NEXT:   R_RISCV_ADD32 <null> 0x0
 @IF-RISCV@; RELOCS-NEXT:   R_RISCV_SUB32 <null> 0x0
 @IF-RISCV@; RELOCS-NEXT:   R_RISCV_ADD32 .L_ZTIi.DW.stub 0x0
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll
@@ -111,7 +111,7 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
 ; Note: RISC-V uses DW_EH_PE_udata4, so the 0xc marker uses 4 bytes instead of 1
 ; CHECK-NEXT:  [[SMALL_CS_DIRECTIVE:(\.byte)|(\.word)]] 12     # (landing pad is a capability)
-; CHECK-NEXT:  .chericap .L_Z8do_catchv$local+(.Ltmp2-.Lfunc_begin0) # jumps to .Ltmp2
+; CHECK-NEXT:  .chericap %code(.L_Z8do_catchv$local+(.Ltmp2-.Lfunc_begin0)) # jumps to .Ltmp2
 ; CHECK-NEXT:  .byte 3                               #   On action: 2
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Lfunc_begin0           # >> Call Site 2 <<
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Lfunc_end0-.Ltmp1             #   Call between .Ltmp1 and .Lfunc_end0
@@ -138,7 +138,7 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 
 ; RELOCS-LABEL: Relocations [
 ; RELOCS-LABEL:  Section ({{.+}}) .rela.gcc_except_table {
-; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY .L_Z8do_catchv$local 0x24
+; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY_CODE .L_Z8do_catchv$local 0x24
 ; RELOCS-NEXT:   R_RISCV_ADD32 .L_ZTIi.DW.stub 0x0
 ; RELOCS-NEXT:   R_RISCV_SUB32 .L0 0x0
 ; RELOCS-NEXT:  }
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll
@@ -111,7 +111,7 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
 ; Note: RISC-V uses DW_EH_PE_udata4, so the 0xc marker uses 4 bytes instead of 1
 ; CHECK-NEXT:  [[SMALL_CS_DIRECTIVE:(\.byte)|(\.word)]] 12     # (landing pad is a capability)
-; CHECK-NEXT:  .chericap .L_Z8do_catchv$local+(.Ltmp2-.Lfunc_begin0) # jumps to .Ltmp2
+; CHECK-NEXT:  .chericap %code(.L_Z8do_catchv$local+(.Ltmp2-.Lfunc_begin0)) # jumps to .Ltmp2
 ; CHECK-NEXT:  .byte 3                               #   On action: 2
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Ltmp1-.Lfunc_begin0           # >> Call Site 2 <<
 ; CHECK-NEXT:  [[CS_DIRECTIVE]] .Lfunc_end0-.Ltmp1             #   Call between .Ltmp1 and .Lfunc_end0
@@ -138,7 +138,7 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 
 ; RELOCS-LABEL: Relocations [
 ; RELOCS-LABEL:  Section ({{.+}}) .rela.gcc_except_table {
-; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY .L_Z8do_catchv$local 0x24
+; RELOCS-NEXT:   R_RISCV_CHERI_CAPABILITY_CODE .L_Z8do_catchv$local 0x24
 ; RELOCS-NEXT:   R_RISCV_ADD32 .L_ZTIi.DW.stub 0x0
 ; RELOCS-NEXT:   R_RISCV_SUB32 .L0 0x0
 ; RELOCS-NEXT:  }
diff --git a/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll b/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll
@@ -64,11 +64,11 @@ declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200)
 
 ; CHECK: .section .gcc_except_table
 ; CHECK: .word 12 # (landing pad is a capability)
-; CHECK-NEXT: .chericap  .L_Z4testv$local+(.Ltmp2-.Lfunc_begin0) # jumps to .Ltmp2
+; CHECK-NEXT: .chericap  %code(.L_Z4testv$local+(.Ltmp2-.Lfunc_begin0)) # jumps to .Ltmp2
 
 ; OBJ-LABEL: Relocation section '.rela.gcc_except_table' at offset
 ; OBJ: Offset             Info             Type                    Symbol's Value   Symbol's Name + Addend
-; OBJ: 0000000000000020 0000000{{.}}000000c1 R_RISCV_CHERI_CAPABILITY
+; OBJ: 0000000000000020 0000000{{.}}000000c3 R_RISCV_CHERI_CAPABILITY_CODE
 
 ; OBJ-LABEL: Symbol table '.symtab' contains
 ; OBJ:    Value          Size Type    Bind   Vis       Ndx Name
