[CHERIoT] Remove all explicit checks for the riscv32cheriot subarchitecture.

It still parses, but we now handle everything related to Cheriot configuration through the
clang driver.

Author: resistor

clang/lib/Basic/Targets/RISCV.cpp

@@ -377,15 +377,6 @@ bool RISCVTargetInfo::initFeatureMap(
     Features["32bit"] = true;
   }
 
-  if (getTriple().getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) {
-    Features["xcheri"] = true;
-    Features["xcheriot"] = true;
-    Features["xcheripurecap"] = true;
-    Features["c"] = true;
-    Features["e"] = true;
-    Features["m"] = true;
-  }
-
   std::vector<std::string> AllFeatures = FeaturesVec;
   auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
   if (!ParseResult) {
@@ -464,7 +455,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
     CapSize = XLen * 2;
   }
   if (ABI.empty())
-    ABI = ISAInfo->computeDefaultABI().str();
+    ABI = ISAInfo->computeDefaultABI(getTriple()).str();
 
   if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;

clang/lib/Basic/Targets/RISCV.h

@@ -84,7 +84,7 @@ class RISCVTargetInfo : public TargetInfo {
   bool HasExperimental = false;
 
 public:
-  RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
+  RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : TargetInfo(Triple) {
     BFloat16Width = 16;
     BFloat16Align = 16;
@@ -99,12 +99,6 @@ class RISCVTargetInfo : public TargetInfo {
     MCountName = "_mcount";
     HasFloat16 = true;
     HasStrictFP = true;
-
-    if (Triple.getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) {
-      CPU = "cheriot";
-      ABI = (Triple.getOS() == llvm::Triple::CheriotRTOS) ? "cheriot"
-                                                          : "cheriot-baremetal";
-    }
   }
 
   bool setCPU(const std::string &Name) override {

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

@@ -306,19 +306,11 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   // rv64e -> lp64e
   // rv64* -> lp64
   std::string Arch = getRISCVArch(Args, Triple);
-  if (Triple.getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) {
-    llvm::Triple::OSType OS = Triple.getOS();
-    if (OS == llvm::Triple::CheriotRTOS)
-      return "cheriot";
-    else if (OS == llvm::Triple::UnknownOS)
-      return "cheriot-baremetal";
-  }
-
   auto ParseResult = llvm::RISCVISAInfo::parseArchString(
       Arch, /* EnableExperimentalExtension */ true);
   // Ignore parsing error, just go 3rd step.
   if (!llvm::errorToBool(ParseResult.takeError()))
-    return (*ParseResult)->computeDefaultABI();
+    return (*ParseResult)->computeDefaultABI(Triple);
 
   // 3. Choose a default based on the triple
   //
@@ -429,8 +421,7 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args,
   // We deviate from GCC's defaults here:
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
-  if (Triple.getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1 ||
-      Triple.getOS() == llvm::Triple::CheriotRTOS)
+  if (Triple.getOS() == llvm::Triple::CheriotRTOS)
     return "rv32emc_xcheriot";
   if (Triple.isRISCV32()) {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
@@ -461,9 +452,13 @@ std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
   if (!CPU.empty())
     return CPU;
 
-  if (Triple.getOS() == llvm::Triple::CheriotRTOS ||
-      Triple.getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1)
+  if (Triple.getOS() == llvm::Triple::CheriotRTOS)
     return "cheriot";
+  if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
+    StringRef ABI = A->getValue();
+    if (ABI == "cheriot" || ABI == "cheriot-baremetal")
+      return "cheriot";
+  }
 
   return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
 }

clang/test/Driver/cheri/cheriot.c

@@ -1,13 +1,10 @@
-// RUN: %clang -target riscv32cheriot -### -c %s 2>&1 | FileCheck %s -check-prefixes BAREMETAL,ALL
-// RUN: %clang -target riscv32cheriot-unknown-unknown -### -c %s 2>&1 | FileCheck %s -check-prefixes BAREMETAL,ALL
+// RUN: %clang -target riscv32cheriot-unknown-unknown -mcpu=cheriot -### -c %s 2>&1 | FileCheck %s -check-prefixes BAREMETAL,ALL
+// RUN: %clang -target riscv32cheriot-unknown-unknown -mabi=cheriot-baremetal -### -c %s 2>&1 | FileCheck %s -check-prefixes BAREMETAL,ALL
 // RUN: %clang -target riscv32cheriot-unknown-cheriotrtos -### -c %s 2>&1 | FileCheck %s -check-prefixes RTOS,ALL
 
 
 // ALL: "-target-cpu" "cheriot"
-// ALL: "-target-feature" "+e"
-// ALL: "-target-feature" "+m"
-// ALL: "-target-feature" "+c"
-// ALL: "-target-feature" "+xcheri"
+// ALL: "-target-feature" "+xcheriot"
 
 // BAREMETAL: "-target-abi" "cheriot-baremetal"
 // RTOS: "-target-abi" "cheriot"

clang/test/SemaCXX/cheri/attr-cheriot-sealed.cpp

@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -std=c++11 -triple riscv32cheriot -verify %s
+// RUN: %clang_cc1 -std=c++11 -triple riscv32cheriot-unknown-cheriotrtos -verify %s
 
 struct test_struct {
     int b;

lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s

@@ -4,7 +4,7 @@
 # RUN: llvm-objdump -d %t.exe | FileCheck %s
 
 	.attribute	4, 16
-	.attribute	5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0_xcheripurecap1p0"
+	.attribute	5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0_xcheripurecap0p0"
 	.section	.text,"ax",@progbits
 	.globl	_start
 	.p2align	1

llvm/include/llvm/TargetParser/RISCVISAInfo.h

@@ -21,6 +21,8 @@
 
 namespace llvm {
 
+class Triple;
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
@@ -66,7 +68,7 @@ class RISCVISAInfo {
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
-  StringRef computeDefaultABI() const;
+  StringRef computeDefaultABI(const llvm::Triple &Triple) const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -92,14 +92,11 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
   auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
   if (!ISAInfo)
     report_fatal_error(ISAInfo.takeError());
-  return getTargetABI((*ISAInfo)->computeDefaultABI(), TT);
+  return getTargetABI((*ISAInfo)->computeDefaultABI(TT), TT);
 }
 
 ABI getTargetABI(StringRef ABIName, const Triple &TT) {
   ABI Default = ABI_Unknown;
-  if (TT.getSubArch() == Triple::RISCV32SubArch_cheriot_v1) {
-    Default = (TT.getOS() == Triple::CheriotRTOS) ? ABI_CHERIOT : ABI_CHERIOT_BAREMETAL;
-  }
 
   auto TargetABI = StringSwitch<ABI>(ABIName)
                        .Case("ilp32", ABI_ILP32)

llvm/lib/TargetParser/RISCVISAInfo.cpp

@@ -13,6 +13,7 @@
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/Triple.h"
 
 #include <array>
 #include <atomic>
@@ -955,10 +956,11 @@ RISCVISAInfo::postProcessAndChecking(std::unique_ptr<RISCVISAInfo> &&ISAInfo) {
   return std::move(ISAInfo);
 }
 
-StringRef RISCVISAInfo::computeDefaultABI() const {
+StringRef RISCVISAInfo::computeDefaultABI(const llvm::Triple &Triple) const {
   if (XLen == 32) {
     if (Exts.count("xcheriot"))
-      return "cheriot";
+      return Triple.getOS() == llvm::Triple::CheriotRTOS ? "cheriot"
+                                                         : "cheriot-baremetal";
     if (Exts.count("e"))
       return "ilp32e";
     if (Exts.count("d"))