[ELF][RISCV] Stop using CSub for capability subtraction

jrtc27 · resistor · commit c13388a62209 · 2025-11-03T21:31:39.000+09:00
This code is currently dead since we emit an all-zeroes PLT header on CHERI-RISC-V, but will soon be used. Fixes: 05652b9 ("[CHERI-RISC-V] Remove CSub")
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
@@ -78,7 +78,6 @@ enum Op {
   CIncOffsetImm = 0x105b,
   CLC_64 = 0x3003,
   CLC_128 = 0x200f,
-  CSub = 0x2800005b,
 
   AUIPCC = 0x17,
   AUICGP = 0x7b,
@@ -272,12 +271,12 @@ void RISCV::writePltHeader(uint8_t *buf) const {
   // (c)sub t1, (c)t1, (c)t3
   // l[wdc] (c)t3, %pcrel_lo(1b)((c)t2); (c)t3 = _dl_runtime_resolve
   // addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
-  // addi t0, t2, %pcrel_lo(1b)
-  // srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
-  // l[wd] t0, Wordsize(t0); t0 = link_map
-  // jr t3
+  // addi/cincoffset (c)t0, (c)t2, %pcrel_lo(1b)
+  // (if shift != 0): srli t1, t1, shift; t1 = &.got.plt[i] - &.got.plt[0]
+  // l[wdc] (c)t0, Ptrsize((c)t0); (c)t0 = link_map
+  // (c)jr (c)t3
+  // (if shift == 0): nop
   uint32_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
-  uint32_t ptrsub = ctx.arg.isCheriAbi ? CSub : SUB;
   uint32_t ptrload = ctx.arg.isCheriAbi ? ctx.arg.is64 ? CLC_128 : CLC_64
                      : ctx.arg.is64     ? LD
                                         : LW;
@@ -287,7 +286,7 @@ void RISCV::writePltHeader(uint8_t *buf) const {
   uint32_t ptrsize =
       ctx.arg.isCheriAbi ? ctx.arg.capabilitySize : ctx.arg.wordsize;
   write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
-  write32le(buf + 4, rtype(ptrsub, X_T1, X_T1, X_T3));
+  write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
   write32le(buf + 8, itype(ptrload, X_T3, X_T2, lo12(offset)));
   write32le(buf + 12, itype(ADDI, X_T1, X_T1, -ctx.target->pltHeaderSize - 12));
   write32le(buf + 16, itype(ptraddi, X_T0, X_T2, lo12(offset)));
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
@@ -64,7 +64,7 @@ ELF_RELOC(R_RISCV_VENDOR,           191)
 // ELF_RELOC(R_RISCV_CUSTOM192,        192)
 // ELF_RELOC(R_RISCV_CUSTOM193,        193)
 ELF_RELOC(R_RISCV_CUSTOM194,        194)
-// ELF_RELOC(R_RISCV_CUSTOM195,        195)
+ELF_RELOC(R_RISCV_CUSTOM195,        195)
 // ELF_RELOC(R_RISCV_CUSTOM196,        196)
 // ELF_RELOC(R_RISCV_CUSTOM197,        197)
 // ELF_RELOC(R_RISCV_CUSTOM198,        198)
diff --git a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s
@@ -40,7 +40,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   c.j undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
   c.jal NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -56,7 +56,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   c.jal undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
   jal zero, NEAR
 # CHECK: c.j {{0x[0-9a-f]+}} <NEAR>
@@ -72,7 +72,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   jal zero, undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
   jal ra, NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -88,7 +88,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   jal ra, undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
   qc.e.j NEAR
 # CHECK: c.j {{0x[0-9a-f]+}} <NEAR>
@@ -104,7 +104,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   qc.e.j undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
   qc.e.jal NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -120,7 +120,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   qc.e.jal undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CHERI_SIZE undef
+# CHECK: R_RISCV_CUSTOM195 undef
 
 
 
diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s
@@ -15,7 +15,7 @@ branch_over_relaxable:
   jal x1, foo
 # CHECK: qc.e.jal 0x0 <branch_over_relaxable>
 # CHECK-NEXT: R_RISCV_VENDOR QUALCOMM
-# CHECK-NEXT: R_RISCV_CHERI_SIZE foo
+# CHECK-NEXT: R_RISCV_CUSTOM195 foo
 # CHECK-NEXT: R_RISCV_RELAX *ABS*
   bne a0, a1, branch_over_relaxable
 # CHECK-NEXT: bne a0, a1, 0x6 <branch_over_relaxable+0x6>
diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s
@@ -21,13 +21,13 @@ this_section:
 # ASM: qc.e.j undef
 # OBJ: qc.e.j 0x0 <this_section>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
 qc.e.j undef
 
 # ASM: qc.e.jal undef
 # OBJ-NEXT: qc.e.jal 0x6 <this_section+0x6>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
 qc.e.jal undef
 
 
@@ -42,26 +42,26 @@ qc.e.jal same_section
 # ASM: qc.e.j same_section_extern
 # OBJ-NEXT: qc.e.j 0x18 <this_section+0x18>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section_extern{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}}
 qc.e.j same_section_extern
 
 # ASM: qc.e.jal same_section_extern
 # OBJ-NEXT: qc.e.jal 0x1e <this_section+0x1e>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section_extern{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}}
 qc.e.jal same_section_extern
 
 
 # ASM: qc.e.j other_section
 # OBJ-NEXT: qc.e.j 0x24 <this_section+0x24>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE other_section{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}}
 qc.e.j other_section
 
 # ASM: qc.e.jal other_section
 # OBJ-NEXT: qc.e.jal 0x2a <this_section+0x2a>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE other_section{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}}
 qc.e.jal other_section
 
 
@@ -81,14 +81,14 @@ same_section_extern:
 # ASM: qc.e.j same_section
 # OBJ: qc.e.j 0x38 <same_section_extern+0x4>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 qc.e.j same_section
 
 # ASM: qc.e.jal same_section
 # OBJ-NEXT: qc.e.jal 0x3e <same_section_extern+0xa>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 qc.e.jal same_section
 
@@ -99,14 +99,14 @@ qc.e.j undef
 # ASM: j undef
 # OBJ: qc.e.j 0x44 <same_section_extern+0x10>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 
 qc.e.jal undef
 # ASM: jal undef
 # OBJ: qc.e.jal 0x4a <same_section_extern+0x16>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 
 .section .text.other, "ax", @progbits
