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[CHERI] Integrate the RISCV Y version of the CHERI register file.
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‎clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,10 @@ void *__capability global_fn_to_cap(void) {
2626
// ASM-MIPS: cgetpcc $c1
2727
// ASM-MIPS-NEXT: ld $1, %got_disp(external_fn)($1)
2828
// ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
29-
// ASM-RISCV: cspecialr ca1, pcc
29+
// ASM-RISCV: cspecialr a1, pcc
3030
// ASM-RISCV: auipc a0, %got_pcrel_hi(external_fn)
3131
// ASM-RISCV-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
32-
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
32+
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
3333
return (__cheri_tocap void *__capability)&external_fn;
3434
}
3535

@@ -46,8 +46,8 @@ void *__capability global_data_to_cap(void) {
4646
// ASM-MIPS-NEXT: csetbounds $c3, $c1, 4
4747
// ASM-RISCV: auipc a0, %got_pcrel_hi(external_global)
4848
// ASM-RISCV-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
49-
// ASM-RISCV-NEXT: cspecialr ca1, ddc
50-
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
49+
// ASM-RISCV-NEXT: cspecialr a1, ddc
50+
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
5151
// We do not set bounds on RISCV
5252
// ASM-RISCV-NOT: csetbounds
5353
return (__cheri_tocap void *__capability)&external_global;
@@ -68,8 +68,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
6868
// ASM-LABEL: fn_ptr_to_cap:
6969
// ASM-MIPS: cgetpcc $c1
7070
// ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
71-
// ASM-RISCV: cspecialr ca1, pcc
72-
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
71+
// ASM-RISCV: cspecialr a1, pcc
72+
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
7373
return (__cheri_tocap void *__capability)fn_ptr;
7474
}
7575

@@ -88,8 +88,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
8888
void *__capability fn_ptr_to_cap_not_smart_enough(void (*fn_ptr)(void)) {
8989
// ASM-LABEL: fn_ptr_to_cap_not_smart_enough:
9090
// ASM-MIPS: cfromddc $c3, $1
91-
// ASM-RISCV: cspecialr ca1, ddc
92-
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
91+
// ASM-RISCV: cspecialr a1, ddc
92+
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
9393
// Note: In this case clang doesn't see that the result is actual a function
9494
// so it uses DDC:
9595
void *tmp = (void *)fn_ptr;
@@ -109,7 +109,7 @@ void *__capability data_ptr_to_cap(int *data_ptr) {
109109
// Note: For data pointers we derive from DDC:
110110
// ASM-LABEL: data_ptr_to_cap:
111111
// ASM-MIPS: cfromddc $c3, $1
112-
// ASM-RISCV: cspecialr ca1, ddc
113-
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
112+
// ASM-RISCV: cspecialr a1, ddc
113+
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
114114
return (__cheri_tocap void *__capability)data_ptr;
115115
}

‎clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ _Atomic(int) x;
44

55
int callFromNotLibcall(void) {
66
// Check that atomic libcalls get the right calling convention at the call site.
7-
// CHECK: auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
8-
// CHECK: clc ct2, %cheriot_compartment_lo_i(.LBB0_2)(ct2)
9-
// CHECK: cjalr ct2
7+
// CHECK: auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
8+
// CHECK: clc t2, %cheriot_compartment_lo_i(.LBB0_2)(t2)
9+
// CHECK: cjalr t2
1010
return __c11_atomic_fetch_add(&x, 1, 5);
1111
}

‎lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,12 @@
1010
.p2align 1
1111
.type _start,@function
1212
_start: # @_Z5entryv
13-
ct.auipcc ct1, %cheriot_compartment_hi(near)
14-
ct.auipcc ct1, %cheriot_compartment_hi(mid)
13+
ct.auipcc t1, %cheriot_compartment_hi(near)
14+
ct.auipcc t1, %cheriot_compartment_hi(mid)
1515

1616
# CHECK: 00012000 <_start>:
17-
# CHECK-NEXT: 12000: 00000317 ct.auipcc ct1, 0x0
18-
# CHECK-NEXT: 12004: 00001317 ct.auipcc ct1, 0x1
17+
# CHECK-NEXT: 12000: 00000317 ct.auipcc t1, 0x0
18+
# CHECK-NEXT: 12004: 00001317 ct.auipcc t1, 0x1
1919

2020
.type near,@object
2121
.p2align 3, 0x0

‎lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -10,33 +10,33 @@
1010
.p2align 1
1111
.type _start,@function
1212
_start: # @_Z5entryv
13-
ct.auipcc ct1, %cheriot_compartment_hi(near)
14-
ct.clc ct1, %cheriot_compartment_lo_i(_start)(ct1)
13+
ct.auipcc t1, %cheriot_compartment_hi(near)
14+
ct.clc t1, %cheriot_compartment_lo_i(_start)(t1)
1515
.MID_BLOCK:
16-
ct.auipcc ct1, %cheriot_compartment_hi(mid)
17-
ct.clc ct1, %cheriot_compartment_lo_i(.MID_BLOCK)(ct1)
16+
ct.auipcc t1, %cheriot_compartment_hi(mid)
17+
ct.clc t1, %cheriot_compartment_lo_i(.MID_BLOCK)(t1)
1818
.CGP_BLOCK:
19-
ct.auipcc ct1, %cheriot_compartment_hi(cgp)
20-
ct.clw ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(ct1)
19+
ct.auipcc t1, %cheriot_compartment_hi(cgp)
20+
ct.clw ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(t1)
2121
.CGP_FAR_BLOCK:
22-
ct.auipcc ct1, %cheriot_compartment_hi(cgp_far)
23-
ct.clw ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(ct1)
22+
ct.auipcc t1, %cheriot_compartment_hi(cgp_far)
23+
ct.clw ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(t1)
2424

2525
# CHECK: 00012000 <_start>:
26-
# CHECK-NEXT: 12000: 00000317 ct.auipcc ct1, 0x0
27-
# CHECK-NEXT: 12004: 02033303 ct.clc ct1, 0x20(ct1)
26+
# CHECK-NEXT: 12000: 00000317 ct.auipcc t1, 0x0
27+
# CHECK-NEXT: 12004: 02033303 ct.clc t1, 0x20(t1)
2828

2929
# CHECK: 00012008 <.MID_BLOCK>:
30-
# CHECK-NEXT: 12008: 00001317 ct.auipcc ct1, 0x1
31-
# CHECK-NEXT: 1200c: 7f833303 ct.clc ct1, 0x7f8(ct1)
30+
# CHECK-NEXT: 12008: 00001317 ct.auipcc t1, 0x1
31+
# CHECK-NEXT: 1200c: 7f833303 ct.clc t1, 0x7f8(t1)
3232

3333
# CHECK: 00012010 <.CGP_BLOCK>:
34-
# CHECK-NEXT: 12010: ffffe37b ct.auicgp ct1, 0xffffe
35-
# CHECK-NEXT: 12014: ffc32083 ct.clw ra, -0x4(ct1)
34+
# CHECK-NEXT: 12010: ffffe37b ct.auicgp t1, 0xffffe
35+
# CHECK-NEXT: 12014: ffc32083 ct.clw ra, -0x4(t1)
3636

3737
# CHECK: 00012018 <.CGP_FAR_BLOCK>:
38-
# CHECK-NEXT: 12018: 0000237b ct.auicgp ct1, 0x2
39-
# CHECK-NEXT: 1201c: 00032083 ct.clw ra, 0x0(ct1)
38+
# CHECK-NEXT: 12018: 0000237b ct.auicgp t1, 0x2
39+
# CHECK-NEXT: 1201c: 00032083 ct.clw ra, 0x0(t1)
4040

4141
.type near,@object
4242
.p2align 3, 0x0

‎lld/test/ELF/cheri/riscv/plt.s‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -44,17 +44,17 @@
4444
# DIS: <_start>:
4545
## Direct call
4646
## foo - . = 0x11020-0x11000 = 32
47-
# DIS-NEXT: 11000: auipcc cra, 0
48-
# DIS-NEXT: cjalr 32(cra)
47+
# DIS-NEXT: 11000: auipcc ra, 0
48+
# DIS-NEXT: cjalr 32(ra)
4949
## bar@plt - . = 0x11050-0x11008 = 72
50-
# DIS-NEXT: 11008: auipcc cra, 0
51-
# DIS-NEXT: cjalr 72(cra)
50+
# DIS-NEXT: 11008: auipcc ra, 0
51+
# DIS-NEXT: cjalr 72(ra)
5252
## bar@plt - . = 0x11050-0x11010 = 64
53-
# DIS-NEXT: 11010: auipcc cra, 0
54-
# DIS-NEXT: cjalr 64(cra)
53+
# DIS-NEXT: 11010: auipcc ra, 0
54+
# DIS-NEXT: cjalr 64(ra)
5555
## weak@plt - . = 0x11060-0x11018 = 72
56-
# DIS-NEXT: 11018: auipcc cra, 0
57-
# DIS-NEXT: cjalr 72(cra)
56+
# DIS-NEXT: 11018: auipcc ra, 0
57+
# DIS-NEXT: cjalr 72(ra)
5858
# DIS: <foo>:
5959
# DIS-NEXT: 11020:
6060

@@ -63,17 +63,17 @@
6363
# DIS-NEXT: ...
6464

6565
## 32-bit: &.captable[bar]-. = 0x12000-0x11050 = 4096*1-80
66-
# DIS: 11050: auipcc ct3, 1
67-
# DIS32-NEXT: clc ct3, -80(ct3)
68-
# DIS64-NEXT: clc ct3, -80(ct3)
69-
# DIS-NEXT: cjalr ct1, ct3
66+
# DIS: 11050: auipcc t3, 1
67+
# DIS32-NEXT: clc t3, -80(t3)
68+
# DIS64-NEXT: clc t3, -80(t3)
69+
# DIS-NEXT: cjalr t1, t3
7070
# DIS-NEXT: nop
7171

7272
## 32-bit: &.captable[weak]-. = 0x12008-0x11060 = 4096*1-88
73-
# DIS: 11060: auipcc ct3, 1
74-
# DIS32-NEXT: clc ct3, -88(ct3)
75-
# DIS64-NEXT: clc ct3, -80(ct3)
76-
# DIS-NEXT: cjalr ct1, ct3
73+
# DIS: 11060: auipcc t3, 1
74+
# DIS32-NEXT: clc t3, -88(t3)
75+
# DIS64-NEXT: clc t3, -80(t3)
76+
# DIS-NEXT: cjalr t1, t3
7777
# DIS-NEXT: nop
7878

7979
.global _start, foo, bar

‎lld/test/ELF/cheri/riscv/tls.s‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -54,40 +54,40 @@
5454
# RV32-SO-CAP-NEXT: 0x00003298 00000000 00000000
5555

5656
# 0x121e0 - 0x111b4 = 0x0102c (GD evar)
57-
# RV32-DIS: 111b4: auipcc ca0, 1
58-
# RV32-DIS-NEXT: cincoffset ca0, ca0, 44
57+
# RV32-DIS: 111b4: auipcc a0, 1
58+
# RV32-DIS-NEXT: cincoffset a0, a0, 44
5959

6060
# 0x121f0 - 0x111bc = 0x01034 (IE evar)
61-
# RV32-DIS: 111bc: auipcc ca0, 1
62-
# RV32-DIS-NEXT: clw a0, 52(ca0)
61+
# RV32-DIS: 111bc: auipcc a0, 1
62+
# RV32-DIS-NEXT: clw a0, 52(a0)
6363

6464
# 0x121e8 - 0x111c4 = 0x01024 (GD lvar)
65-
# RV32-DIS: 111c4: auipcc ca0, 1
66-
# RV32-DIS-NEXT: cincoffset ca0, ca0, 36
65+
# RV32-DIS: 111c4: auipcc a0, 1
66+
# RV32-DIS-NEXT: cincoffset a0, a0, 36
6767

6868
# 0x121f4 - 0x111cc = 0x01028 (IE lvar)
69-
# RV32-DIS: 111cc: auipcc ca0, 1
70-
# RV32-DIS-NEXT: clw a0, 40(ca0)
69+
# RV32-DIS: 111cc: auipcc a0, 1
70+
# RV32-DIS-NEXT: clw a0, 40(a0)
7171

7272
# RV32-DIS: 111d4: lui a0, 0
73-
# RV32-DIS-NEXT: cincoffset ca0, ctp, a0
74-
# RV32-DIS-NEXT: cincoffset ca0, ca0, 4
73+
# RV32-DIS-NEXT: cincoffset a0, tp, a0
74+
# RV32-DIS-NEXT: cincoffset a0, a0, 4
7575

7676
# 0x3288 - 0x1210 = 0x2078 (GD evar)
77-
# RV32-SO-DIS: 1210: auipcc ca0, 2
78-
# RV32-SO-DIS-NEXT: cincoffset ca0, ca0, 120
77+
# RV32-SO-DIS: 1210: auipcc a0, 2
78+
# RV32-SO-DIS-NEXT: cincoffset a0, a0, 120
7979

8080
# 0x3298 - 0x1218 = 0x2080 (IE evar)
81-
# RV32-SO-DIS: 1218: auipcc ca0, 2
82-
# RV32-SO-DIS-NEXT: clw a0, 128(ca0)
81+
# RV32-SO-DIS: 1218: auipcc a0, 2
82+
# RV32-SO-DIS-NEXT: clw a0, 128(a0)
8383

8484
# 0x3290 - 0x1220 = 0x2070 (GD lvar)
85-
# RV32-SO-DIS: 1220: auipcc ca0, 2
86-
# RV32-SO-DIS-NEXT: cincoffset ca0, ca0, 112
85+
# RV32-SO-DIS: 1220: auipcc a0, 2
86+
# RV32-SO-DIS-NEXT: cincoffset a0, a0, 112
8787

8888
# 0x329c - 0x1228 = 0x2074 (IE lvar)
89-
# RV32-SO-DIS: 1228: auipcc ca0, 2
90-
# RV32-SO-DIS-NEXT: clw a0, 116(ca0)
89+
# RV32-SO-DIS: 1228: auipcc a0, 2
90+
# RV32-SO-DIS-NEXT: clw a0, 116(a0)
9191

9292
# RV64-REL: .rela.dyn {
9393
# RV64-REL-NEXT: 0x122F0 R_RISCV_TLS_DTPMOD64 evar 0x0
@@ -114,55 +114,55 @@
114114
# RV64-SO-CAP-NEXT: 0x00003440 00000000 00000000 00000000 00000000
115115

116116
# 0x122f0 - 0x112b8 = 0x01038 (GD evar)
117-
# RV64-DIS: 112b8: auipcc ca0, 1
118-
# RV64-DIS-NEXT: cincoffset ca0, ca0, 56
117+
# RV64-DIS: 112b8: auipcc a0, 1
118+
# RV64-DIS-NEXT: cincoffset a0, a0, 56
119119

120120
# 0x12310 - 0x112c0 = 0x01050 (IE evar)
121-
# RV64-DIS: 112c0: auipcc ca0, 1
122-
# RV64-DIS-NEXT: cld a0, 80(ca0)
121+
# RV64-DIS: 112c0: auipcc a0, 1
122+
# RV64-DIS-NEXT: cld a0, 80(a0)
123123

124124
# 0x12300 - 0x112c8 = 0x01038 (GD lvar)
125-
# RV64-DIS: 112c8: auipcc ca0, 1
126-
# RV64-DIS-NEXT: cincoffset ca0, ca0, 56
125+
# RV64-DIS: 112c8: auipcc a0, 1
126+
# RV64-DIS-NEXT: cincoffset a0, a0, 56
127127

128128
# 0x12318 - 0x112d0 = 0x01048 (IE lvar)
129-
# RV64-DIS: 112d0: auipcc ca0, 1
130-
# RV64-DIS-NEXT: cld a0, 72(ca0)
129+
# RV64-DIS: 112d0: auipcc a0, 1
130+
# RV64-DIS-NEXT: cld a0, 72(a0)
131131

132132
# RV64-DIS: 112d8: lui a0, 0
133-
# RV64-DIS-NEXT: cincoffset ca0, ctp, a0
134-
# RV64-DIS-NEXT: cincoffset ca0, ca0, 4
133+
# RV64-DIS-NEXT: cincoffset a0, tp, a0
134+
# RV64-DIS-NEXT: cincoffset a0, a0, 4
135135

136136
# 0x3420 - 0x1350 = 0x20d0 (GD evar)
137-
# RV64-SO-DIS: 1350: auipcc ca0, 2
138-
# RV64-SO-DIS-NEXT: cincoffset ca0, ca0, 208
137+
# RV64-SO-DIS: 1350: auipcc a0, 2
138+
# RV64-SO-DIS-NEXT: cincoffset a0, a0, 208
139139

140140
# 0x3440 - 0x1358 = 0x20e8 (IE evar)
141-
# RV64-SO-DIS: 1358: auipcc ca0, 2
142-
# RV64-SO-DIS-NEXT: cld a0, 232(ca0)
141+
# RV64-SO-DIS: 1358: auipcc a0, 2
142+
# RV64-SO-DIS-NEXT: cld a0, 232(a0)
143143

144144
# 0x3430 - 0x1360 = 0x20d0 (GD lvar)
145-
# RV64-SO-DIS: 1360: auipcc ca0, 2
146-
# RV64-SO-DIS-NEXT: cincoffset ca0, ca0, 208
145+
# RV64-SO-DIS: 1360: auipcc a0, 2
146+
# RV64-SO-DIS-NEXT: cincoffset a0, a0, 208
147147

148148
# 0x3448 - 0x1368 = 0x20e0 (IE lvar)
149-
# RV64-SO-DIS: 1368: auipcc ca0, 2
150-
# RV64-SO-DIS-NEXT: cld a0, 224(ca0)
149+
# RV64-SO-DIS: 1368: auipcc a0, 2
150+
# RV64-SO-DIS-NEXT: cld a0, 224(a0)
151151

152152
.global _start
153153
_start:
154-
clc.tls.gd ca0, evar
154+
clc.tls.gd a0, evar
155155

156-
cla.tls.ie a0, evar, ca0
156+
cla.tls.ie a0, evar, a0
157157

158-
clc.tls.gd ca0, lvar
158+
clc.tls.gd a0, lvar
159159

160-
cla.tls.ie a0, lvar, ca0
160+
cla.tls.ie a0, lvar, a0
161161

162162
.if PIC == 0
163163
lui a0, %tprel_hi(lvar)
164-
cincoffset ca0, ctp, a0, %tprel_cincoffset(lvar)
165-
cincoffset ca0, ca0, %tprel_lo(lvar)
164+
cincoffset a0, tp, a0, %tprel_cincoffset(lvar)
165+
cincoffset a0, a0, %tprel_lo(lvar)
166166
.endif
167167

168168
.tbss

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -351,9 +351,9 @@ class RISCVAsmParser : public MCTargetAsmParser {
351351
// significantly improves diagnostics and allows reusing the same register
352352
// names for capmode vs non-capmode.
353353
FeatureBitset CapModeSet =
354-
ComputeAvailableFeatures({RISCV::FeatureCapMode});
354+
ComputeAvailableFeatures({RISCV::FeatureVendorXCheriPureCap});
355355
FeatureBitset NoCapModeSet = ComputeAvailableFeatures({});
356-
// setConflictingFeatures(CapModeSet ^ NoCapModeSet);
356+
setConflictingFeatures(CapModeSet ^ NoCapModeSet);
357357

358358
auto ABIName = StringRef(Options.ABIName);
359359
if (ABIName.ends_with("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
@@ -549,9 +549,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
549549
RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
550550
}
551551

552-
bool isGPCR() const {
552+
bool isYGPR() const {
553553
return Kind == KindTy::Register &&
554-
RISCVMCRegisterClasses[RISCV::GPCRRegClassID].contains(Reg.RegNum);
554+
RISCVMCRegisterClasses[RISCV::YGPRRegClassID].contains(Reg.RegNum);
555555
}
556556

557557
bool isGPRPair() const {
@@ -1464,6 +1464,11 @@ static MCRegister convertFPR64ToFPR128(MCRegister Reg) {
14641464
return Reg - RISCV::F0_D + RISCV::F0_Q;
14651465
}
14661466

1467+
static MCRegister convertGPRToYGPR(MCRegister Reg) {
1468+
assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid register");
1469+
return Reg - RISCV::X0 + RISCV::X0_Y;
1470+
}
1471+
14671472
static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
14681473
unsigned Kind) {
14691474
unsigned RegClassID;
@@ -1492,6 +1497,17 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
14921497
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
14931498
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
14941499

1500+
bool WantsYReg = Kind == MCK_YGPR || Kind == MCK_YGPRC ||
1501+
Kind == MCK_YGPRTC || Kind == MCK_YGPRE ||
1502+
Kind == MCK_YGPRNoX0X1 || Kind == MCK_YGPRNoX0 ||
1503+
Kind == MCK_YGPRX0IsDDC;
1504+
1505+
if (Op.isGPR() && WantsYReg) {
1506+
// GPR and capability GPR use the same register names, convert if required.
1507+
Op.Reg.RegNum = convertGPRToYGPR(Reg);
1508+
return Match_Success;
1509+
}
1510+
14951511
if (IsRegFPR64 && Kind == MCK_FPR128) {
14961512
Op.Reg.RegNum = convertFPR64ToFPR128(Reg);
14971513
return Match_Success;
@@ -4245,7 +4261,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst,
42454261
assert(Inst.getOpcode() == RISCV::PseudoCIncOffsetTPRel &&
42464262
"Invalid instruction");
42474263
assert(Inst.getOperand(1).isReg() && "Unexpected first operand kind");
4248-
if (Inst.getOperand(1).getReg() != RISCV::C4) {
4264+
if (Inst.getOperand(1).getReg() != RISCV::X4_Y) {
42494265
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc();
42504266
return Error(ErrorLoc, "the first input operand must be ctp/c4 when using "
42514267
"%tprel_cincoffset modifier");

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