[RISCV] Remove zvk uimm constraints

Since the spec doesn't describe these behaviors as invalid,
the llvm-mc should just make them take care by hardware.

Differential Revision: https://reviews.llvm.org/D155669

Author: 4vtomat

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1546,15 +1546,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidRnumArg: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
   }
-  case Match_InvalidRnumArg_0_7: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 7);
-  }
-  case Match_InvalidRnumArg_1_10: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, 10);
-  }
-  case Match_InvalidRnumArg_2_14: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 2, 14);
-  }
   }
 
   llvm_unreachable("Unknown match type detected!");

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

@@ -174,13 +174,13 @@ let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
   defm VAESDM     : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
   defm VAESEF     : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
   defm VAESEM     : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
-  def  VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>;
-  def  VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>;
+  def  VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", uimm5>;
+  def  VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", uimm5>;
   def  VAESZ_VS   : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
 } // Predicates = [HasStdExtZvkned]
 
 let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
-  def  VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
+  def  VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>;
   defm VSM4R    : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
 } // Predicates = [HasStdExtZvksed]
 

llvm/test/MC/RISCV/rvv/zvkned-invalid.s

@@ -62,12 +62,24 @@ vaeskf1.vi v10, v9, 1
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 77 a5 90 8a   <unknown>
 
+vaeskf1.vi v10, v9, 31
+# CHECK-INST: vaeskf1.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 9f 8a   <unknown>
+
 vaeskf2.vi v10, v9, 2
 # CHECK-INST: vaeskf2.vi v10, v9, 2
 # CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 77 25 91 aa   <unknown>
 
+vaeskf2.vi v10, v9, 31
+# CHECK-INST: vaeskf2.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 9f aa   <unknown>
+
 vaesz.vs v10, v9
 # CHECK-INST: vaesz.vs v10, v9
 # CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]

llvm/test/MC/RISCV/rvv/zvkned.s

@@ -14,6 +14,12 @@ vsm4k.vi v10, v9, 7
 # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
 # CHECK-UNKNOWN: 77 a5 93 86   <unknown>
 
+vsm4k.vi v10, v9, 31
+# CHECK-INST: vsm4k.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
+# CHECK-UNKNOWN: 77 a5 9f 86   <unknown>
+
 vsm4r.vv v10, v9
 # CHECK-INST: vsm4r.vv v10, v9
 # CHECK-ENCODING: [0x77,0x25,0x98,0xa2]