[CHERIoT] Clean up direct references to the "cheriot" CPU name in favor of FeatureVendorXCheriot1

Author: resistor

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1828,7 +1828,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
         "an integer in the range");
   case Match_InvalidUImm20AUIPC:
     // FIXME: This should be keyed off an Xcheriot feature, not a CPU name.
-    if (getSTI().getCPU() == "cheriot")
+    if (getSTI().hasFeature(RISCV::FeatureVendorXCheriot1))
       return generateImmOutOfRangeError(
           Operands, ErrorInfo, 0, (1 << 20) - 1,
           "operand must be a symbol with a "

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -147,9 +147,9 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
     report_fatal_error("RV32 and RV64 can't be combined");
   if (FeatureBits[RISCV::FeatureVendorXCheriot1]) {
     if (!FeatureBits[RISCV::FeatureVendorXCheri])
-      report_fatal_error("XCheriotV1 extension requires XCheri extension");
+      report_fatal_error("XCheriot1 extension requires XCheri extension");
     if (!FeatureBits[RISCV::FeatureCapMode])
-      report_fatal_error("XCheriotV1 extension requires CapMode");
+      report_fatal_error("XCheriot1 extension requires CapMode");
   }
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVCompressedCap.cpp

@@ -18,7 +18,7 @@ namespace RISCVCompressedCap {
 
 static inline CompressedCapability::CapabilityFormat
 GetCapabilitySize(const MCSubtargetInfo &STI) {
-  if (STI.getCPU() == "cheriot")
+  if (STI.hasFeature(RISCV::FeatureVendorXCheriot1))
     return CompressedCapability::Cheriot64;
 
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

@@ -108,8 +108,9 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_CHERI_CJAL;
     case RISCV::fixup_riscv_ccall: {
       const auto *STI = Ctx.getSubtargetInfo();
-      if (STI->getCPU() == "cheriot" || STI->getTargetTriple().getSubArch() ==
-                                            Triple::RISCV32SubArch_cheriot_v1)
+      if (STI->hasFeature(RISCV::FeatureVendorXCheriot1) ||
+          STI->getTargetTriple().getSubArch() ==
+              Triple::RISCV32SubArch_cheriot_v1)
         return ELF::R_RISCV_CHERIOT_CCALL;
       return ELF::R_RISCV_CHERI_CCALL;
     }