[CHERI] Remove support for CHERI256.

Author: resistor

lld/test/ELF/cheri/cap-table/Inputs/interposing_table.o

@@ -1,17 +1,10 @@
-
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi purecap -position-independent -filetype=obj %s -o %t-cheri256-main.o
 # RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi purecap -position-independent -filetype=obj %s -o %t-cheri128-main.o
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi n64 -position-independent -filetype=obj %s -o %t-cheri256-hybrid-main.o
 # RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi n64 -position-independent -filetype=obj %s -o %t-cheri128-hybrid-main.o
 # RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=beri     -target-abi n64 -position-independent -filetype=obj %s -o %t-beri-main.o
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi purecap -position-independent -filetype=obj %S/../Inputs/mips-dynamic.s -o %t-cheri256-lib.o
 # RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi purecap -position-independent -filetype=obj %S/../Inputs/mips-dynamic.s -o %t-cheri128-lib.o
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi n64 -position-independent -filetype=obj %S/../Inputs/mips-dynamic.s -o %t-cheri256-hybrid-lib.o
 # RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi n64 -position-independent -filetype=obj %S/../Inputs/mips-dynamic.s -o %t-cheri128-hybrid-lib.o
 # RUN: llvm-readobj -h %t-cheri128-main.o | FileCheck --check-prefix=CHERI128-FLAGS %s
-# RUN: llvm-readobj -h %t-cheri256-main.o | FileCheck --check-prefix=CHERI256-FLAGS %s
 # RUN: llvm-readobj -h %t-cheri128-hybrid-main.o | FileCheck --check-prefix=CHERI128-HYBRID-FLAGS %s
-# RUN: llvm-readobj -h %t-cheri256-hybrid-main.o | FileCheck --check-prefix=CHERI256-HYBRID-FLAGS %s
 
 
 # Check that setting an explicit CHERI emulation overrides the target ABI from the first .o:
@@ -34,23 +27,15 @@
 # RUN:         %S/../Inputs/mips-dynamic.s -mcpu=mips4 -o %t-mips4.o
 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-freebsd \
 # RUN:         %S/../Inputs/mips-dynamic.s -mcpu=beri -o %t-beri.o
-# RUN: not ld.lld %t-cheri256-main.o %t-mips64.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI256-vs-MIPS %s
 # RUN: not ld.lld %t-cheri128-main.o %t-mips64.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI128-vs-MIPS %s
-# RUN: not ld.lld %t-cheri256-main.o %t-cheri128-lib.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI256-vs-CHERI128 %s
-# RUN: not ld.lld %t-cheri128-main.o %t-cheri256-lib.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI128-vs-CHERI256 %s
-# RUN: not ld.lld %t-cheri256-main.o %t-cheri256-hybrid-lib.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI256-vs-CHERI256-HYBRID %s
 # RUN: not ld.lld %t-cheri128-main.o %t-cheri128-hybrid-lib.o -o %t.exe 2>&1 | FileCheck -check-prefix=CHERI128-vs-CHERI128-HYBRID %s
 
 # linking plain mips with hybrid results in a hybrid binary:
-# RUN: ld.lld %t-cheri256-hybrid-main.o %t-mips4.o -o %t.exe
-# RUN: llvm-readobj -h %t.exe | FileCheck --check-prefix=CHERI256-HYBRID-FLAGS %s
 # RUN: ld.lld %t-cheri128-hybrid-main.o %t-mips4.o -o %t.exe
 # RUN: llvm-readobj -h %t.exe | FileCheck --check-prefix=CHERI128-HYBRID-FLAGS %s
 # Same for -mcpu=beri
 # RUN: ld.lld %t-cheri128-hybrid-main.o %t-beri.o -o %t.exe
 # RUN: llvm-readobj -h %t.exe | FileCheck --check-prefix=CHERI128-HYBRID-FLAGS %s
-# RUN: ld.lld %t-cheri256-hybrid-main.o %t-beri.o -o %t.exe
-# RUN: llvm-readobj -h %t.exe | FileCheck --check-prefix=CHERI256-HYBRID-FLAGS %s
 
 
 # Should be able to link beri with MIPS4
@@ -65,7 +50,6 @@
 
 # but not if the plain MIPS arch is a superset of the cheri arch
 # RUN: not ld.lld %t-cheri128-hybrid-main.o %t-mips64.o -o %t.exe 2>&1 | FileCheck -DCHERI_TYPE=cheri128 -check-prefix CHERI-MIPS4-vs-MIPS64 %s
-# RUN: not ld.lld %t-cheri256-hybrid-main.o %t-mips64.o -o %t.exe 2>&1 | FileCheck -DCHERI_TYPE=cheri256 -check-prefix CHERI-MIPS4-vs-MIPS64 %s
 # CHERI-MIPS4-vs-MIPS64: incompatible target ISA:
 # CHERI-MIPS4-vs-MIPS64-NEXT: {{.+}}-[[CHERI_TYPE]]-hybrid-main.o: mips4 ([[CHERI_TYPE]])
 # CHERI-MIPS4-vs-MIPS64-NEXT: {{.+}}-mips64.o: mips64
@@ -75,7 +59,6 @@
 # because -mcpu=mips4 doesn't schedule loads sensibly
 # RUN: not ld.lld --fatal-warnings %t-beri-main.o %t-mips4.o -o /dev/null 2>&1 | FileCheck %s -check-prefix BERI-NON-BERI -DARCH=beri
 # RUN: not ld.lld --fatal-warnings %t-cheri128-hybrid-main.o %t-mips4.o -o /dev/null 2>&1 | FileCheck %s -check-prefix BERI-NON-BERI -DARCH=cheri128
-# RUN: not ld.lld --fatal-warnings %t-cheri256-hybrid-main.o %t-mips4.o -o /dev/null 2>&1 | FileCheck %s -check-prefix BERI-NON-BERI -DARCH=cheri256
 
 // BERI-NON-BERI: ld.lld: error: linking files compiled for BERI/CHERI and non-BERI/CHERI can result in surprising performance:
 // BERI-NON-BERI-NEXT: >>> {{.+}}cheri-elf-flags-err.s.tmp-{{.+}}-main.o: mips4 ([[ARCH]])
@@ -96,13 +79,6 @@ __start:
 # BERI-FLAGS-NEXT:    EF_MIPS_CPIC (0x4)
 # BERI-FLAGS-NEXT:    EF_MIPS_MACH_BERI (0xBE0000)
 # BERI-FLAGS-NEXT:  ]
-# CHERI256-FLAGS:      Machine: EM_MIPS (0x8)
-# CHERI256-FLAGS:      Flags [
-# CHERI256-FLAGS-NEXT:    EF_MIPS_ABI_CHERIABI (0xC000)
-# CHERI256-FLAGS-NEXT:    EF_MIPS_ARCH_4 (0x30000000)
-# CHERI256-FLAGS-NEXT:    EF_MIPS_CPIC (0x4)
-# CHERI256-FLAGS-NEXT:    EF_MIPS_MACH_CHERI256 (0xC20000)
-# CHERI256-FLAGS-NEXT:  ]
 # CHERI128-FLAGS:      Machine: EM_MIPS (0x8)
 # CHERI128-FLAGS:      Flags [
 # CHERI128-FLAGS-NEXT:    EF_MIPS_ABI_CHERIABI (0xC000)
@@ -111,31 +87,16 @@ __start:
 # CHERI128-FLAGS-NEXT:    EF_MIPS_MACH_CHERI128 (0xC10000)
 # CHERI128-FLAGS-NEXT:  ]
 
-# CHERI256-HYBRID-FLAGS:      Machine: EM_MIPS (0x8)
-# CHERI256-HYBRID-FLAGS:      Flags [
-# CHERI256-HYBRID-FLAGS-NEXT:    EF_MIPS_ARCH_4 (0x30000000)
-# CHERI256-HYBRID-FLAGS-NEXT:    EF_MIPS_CPIC (0x4)
-# CHERI256-HYBRID-FLAGS-NEXT:    EF_MIPS_MACH_CHERI256 (0xC20000)
-# CHERI256-HYBRID-FLAGS-NEXT:  ]
 # CHERI128-HYBRID-FLAGS:      Machine: EM_MIPS (0x8)
 # CHERI128-HYBRID-FLAGS:      Flags [
 # CHERI128-HYBRID-FLAGS-NEXT:    EF_MIPS_ARCH_4 (0x30000000)
 # CHERI128-HYBRID-FLAGS-NEXT:    EF_MIPS_CPIC (0x4)
 # CHERI128-HYBRID-FLAGS-NEXT:    EF_MIPS_MACH_CHERI128 (0xC10000)
 # CHERI128-HYBRID-FLAGS-NEXT:  ]
 
-# CHERI256-vs-MIPS: {{.*}}/cheri-elf-flags-err.s.tmp-mips64.o: ABI 'n64' is incompatible with target ABI 'purecap'
 # CHERI128-vs-MIPS: {{.*}}/cheri-elf-flags-err.s.tmp-mips64.o: ABI 'n64' is incompatible with target ABI 'purecap'
-# CHERI256-vs-CHERI128: incompatible target ISA:
-# CHERI256-vs-CHERI128-NEXT: {{.+}}-cheri256-main.o: mips4 (cheri256)
-# CHERI256-vs-CHERI128-NEXT: {{.+}}-cheri128-lib.o: mips4 (cheri128)
-# CHERI128-vs-CHERI256: incompatible target ISA:
-# CHERI128-vs-CHERI256-NEXT: {{.+}}-cheri128-main.o: mips4 (cheri128)
-# CHERI128-vs-CHERI256-NEXT: {{.+}}-cheri256-lib.o: mips4 (cheri256)
-# CHERI256-vs-CHERI256-HYBRID: {{.*}}/cheri-elf-flags-err.s.tmp-cheri256-hybrid-lib.o: ABI 'n64' is incompatible with target ABI 'purecap'
 # CHERI128-vs-CHERI128-HYBRID: {{.*}}/cheri-elf-flags-err.s.tmp-cheri128-hybrid-lib.o: ABI 'n64' is incompatible with target ABI 'purecap'
 
 # TODO: should those files actually link?
-# CHERI256-HYBRID-vs-MIPS: target ISA 'cheri256' is incompatible with 'mips64': {{.*}}/cheri-elf-flags-err.s.tmp-mips64.o
 # CHERI128-HYBRID-vs-MIPS: target ISA 'cheri128' is incompatible with 'mips64': {{.*}}/cheri-elf-flags-err.s.tmp-mips64.o
 

lld/test/ELF/cheri/cap-table/interposing_table.c

@@ -1,5 +1,5 @@
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi purecap -position-independent -filetype=obj -defsym=FIRST=1 -o %t1.o %s
-# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri256 -target-abi purecap -position-independent -filetype=obj -defsym=FIRST=0 -o %t2.o %s
+# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi purecap -position-independent -filetype=obj -defsym=FIRST=1 -o %t1.o %s
+# RUN: llvm-mc -triple=mips64-unknown-freebsd -mcpu=cheri128 -target-abi purecap -position-independent -filetype=obj -defsym=FIRST=0 -o %t2.o %s
 # RUN: ld.lld %t1.o %t2.o -shared -o %t.so
 # RUN: llvm-objdump --cap-relocs -s -t %t.so | FileCheck %s
 
@@ -20,11 +20,9 @@ cap:
 
 # CHECK-LABEL: SYMBOL TABLE:
 # CHECK: 0000000000000000         *UND*		 0000000000000000 foo
-# CHECK: 0000000000020400 g       .data		 0000000000000000 cap
-#                   ^----- Ensure that this is aligned to 0x20
+# CHECK: 00000000000203f0 g       .data		 0000000000000000 cap
+#                   ^----- Ensure that this is aligned to 0x10
 
 # CHECK-LABEL: Contents of section .data:
 # CHECK-NEXT:  203e0 00000000 00001234 00000000 00000000
-# CHECK-NEXT:  203f0 00000000 00000000 00000000 00000000
-# CHECK-NEXT:  20400 00000000 00000000 cacacaca cacacaca
-# CHECK-NEXT:  20410 cacacaca cacacaca cacacaca cacacaca
+# CHECK-NEXT:  203f0 00000000 00000000 cacacaca cacacaca

lld/test/ELF/cheri/cheri-elf-flags-err.s

@@ -3547,9 +3547,6 @@ class LLVM_ABI TargetLoweringBase {
   // Return true if the target has a capability set address instruction.
   virtual bool hasCapabilitySetAddress() const { return false; }
   MVT cheriCapabilityType() const { return CapType; }
-  bool cheriCapabilityTypeHasPreciseBounds() const {
-    return CapTypeHasPreciseBounds;
-  }
   bool supportsUnalignedCapabilityMemOps() const {
     return SupportsUnalignedCapabilityMemOps;
   }
@@ -3985,10 +3982,6 @@ class LLVM_ABI TargetLoweringBase {
   /// Should be one of c64/c128/c256
   MVT CapType = MVT();
 
-  /// Whether the CHERI capability type supports precise bounds for any
-  /// allocation. Defaults to false for safety over efficiency.
-  bool CapTypeHasPreciseBounds = false;
-
   /// Whether CHERI Capability loads/stores can be used with unaligned addresses
   /// This makes it possible to do a tag-preserving copy even if the alignment
   /// is not statically known to be at least capability aligned.

lld/test/ELF/cheri/chericap-alignment.s

@@ -352,8 +352,7 @@ def amdgpuBufferStridedPointer : ValueType<192, 240>;
 def aarch64mfp8 : ValueType<8,  241>;  // 8-bit value in FPR (AArch64)
 
 def c64  : VTCapability<64,  !add(aarch64mfp8.Value, 1)>;  // 64-bit capability value
-def c128 : VTCapability<128, !add(c64.Value,   1)>;  // 128-bit capability value
-def c256 : VTCapability<256, !add(c128.Value,  1)>;  // 256-bit capability value
+def c128 : VTCapability<128, !add(c64.Value, 1)>; // 128-bit capability value
 
 // Pseudo valuetype mapped to the current capability pointer size.
 def cPTR       : VTAny<247>;

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -467,8 +467,6 @@ namespace llvm {
         return MVT::c64;
       case 128:
         return MVT::c128;
-      case 256:
-        return MVT::c256;
       }
     }
 

llvm/include/llvm/CodeGen/ValueTypes.td

@@ -189,14 +189,12 @@ class CheriBoundAllocasImpl : public InstVisitor<CheriBoundAllocasImpl> {
 
       // For imprecise capabilities, we need to increase the alignment for
       // on-stack allocations to ensure that we can create precise bounds.
-      if (!TLI->cheriCapabilityTypeHasPreciseBounds()) {
-        // If not a constant then definitely a DYNAMIC_STACKALLOC; alignment
-        // requirements will be added later during legalisation.
-        if (ConstantInt *CI = dyn_cast<ConstantInt>(ArraySize)) {
-          uint64_t AllocaSize = DL.getTypeAllocSize(AllocationTy);
-          AllocaSize *= CI->getValue().getLimitedValue();
-          ForcedAlignment = TLI->getAlignmentForPreciseBounds(AllocaSize);
-        }
+      // If not a constant then definitely a DYNAMIC_STACKALLOC; alignment
+      // requirements will be added later during legalisation.
+      if (ConstantInt *CI = dyn_cast<ConstantInt>(ArraySize)) {
+        uint64_t AllocaSize = DL.getTypeAllocSize(AllocationTy);
+        AllocaSize *= CI->getValue().getLimitedValue();
+        ForcedAlignment = TLI->getAlignmentForPreciseBounds(AllocaSize);
       }
       if (ForcedAlignment > AI->getAlign())
         AI->setAlignment(ForcedAlignment);

llvm/include/llvm/CodeGenTypes/MachineValueType.h

@@ -1835,18 +1835,11 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
                             SizeVT);
 
     Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, SizeVT, GetAddr, SP);
-
-    if (TLI.cheriCapabilityTypeHasPreciseBounds()) {
-      Tmp2 = Size;
-      Tmp3 = DAG.getConstant(-Alignment.value(), dl, SizeVT);
-    } else {
-      Tmp2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, SizeVT, CRRL, Size);
-      Tmp3 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, SizeVT, CRAM, Size);
-    }
+    Tmp2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, SizeVT, CRRL, Size);
+    Tmp3 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, SizeVT, CRAM, Size);
 
     Tmp1 = DAG.getNode(Opc, dl, SizeVT, Tmp1, Tmp2);
-    if (Alignment > StackAlign || !TLI.cheriCapabilityTypeHasPreciseBounds())
-      Tmp1 = DAG.getNode(ISD::AND, dl, SizeVT, Tmp1, Tmp3);
+    Tmp1 = DAG.getNode(ISD::AND, dl, SizeVT, Tmp1, Tmp3);
 
     Tmp1 =
       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, SetAddr, SP, Tmp1);

llvm/lib/CodeGen/CheriBoundAllocas.cpp

@@ -8514,7 +8514,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
   // TODO: the frontend/optimization passes probably shouldn't emit
   //  must-preserve-tags for such small memcpys
   auto CapTy = TLI.cheriCapabilityType();
-  if (CapTy.isValid() && !Op.isMemset()) {
+  if (DL.hasCheriCapabilities() && CapTy.isValid() && !Op.isMemset()) {
     const uint64_t CapSize = CapTy.getStoreSize();
     if (PreserveTags == PreserveCheriTags::Required && !ReachedLimit &&
         Size >= CapSize && (!FoundLowering || !MemOps[0].isFatPointer())) {
@@ -8743,7 +8743,7 @@ static SDValue getMemmoveLoadsAndStores(
   // TODO: the frontend probably shouldn't emit must-preserve-tags for such
   // small memcpys
   auto CapTy = TLI.cheriCapabilityType();
-  if (CapTy.isValid()) {
+  if (DL.hasCheriCapabilities() && CapTy.isValid()) {
     const uint64_t CapSize = CapTy.getStoreSize();
     if (PreserveTags == PreserveCheriTags::Required && !ReachedLimit &&
         Size >= CapSize && (!FoundLowering || !MemOps[0].isFatPointer())) {