[BinaryFormat][RISCV] Reserve R_RISCV_CHERI_CAPABILITY_CODE

jrtc27 · resistor · commit f0660e128105 · 2025-11-13T11:41:43.000-08:00
For non-c18n runtimes this is the same as R_RISCV_CHERI_CAPABILITY, but
for c18n runtimes this marks capabilities that must not be wrapped in a
trampoline as they must point directly to the code in question.
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
@@ -64,7 +64,7 @@ ELF_RELOC(R_RISCV_VENDOR,           191)
 // ELF_RELOC(R_RISCV_CUSTOM192,        192)
 // ELF_RELOC(R_RISCV_CUSTOM193,        193)
 // ELF_RELOC(R_RISCV_CUSTOM194,        194)
-ELF_RELOC(R_RISCV_CUSTOM195,        195)
+// ELF_RELOC(R_RISCV_CUSTOM195,        195)
 // ELF_RELOC(R_RISCV_CUSTOM196,        196)
 // ELF_RELOC(R_RISCV_CUSTOM197,        197)
 // ELF_RELOC(R_RISCV_CUSTOM198,        198)
@@ -130,7 +130,7 @@ ELF_RELOC(R_RISCV_CUSTOM255,        255)
 ELF_RELOC(R_RISCV_CHERI_CAPTAB_PCREL_HI20,        192)
 ELF_RELOC(R_RISCV_CHERI_CAPABILITY,               193)
 ELF_RELOC(R_RISCV_FUNC_RELATIVE,                  194)
-// 195 reserved
+ELF_RELOC(R_RISCV_CHERI_CAPABILITY_CODE,          195)
 ELF_RELOC(R_RISCV_CHERI_TPREL_CINCOFFSET,         196) // Deprecated
 ELF_RELOC(R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20, 197) // Deprecated
 ELF_RELOC(R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20, 198) // Deprecated
diff --git a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s
@@ -40,7 +40,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   c.j undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
   c.jal NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -56,7 +56,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   c.jal undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
   jal zero, NEAR
 # CHECK: c.j {{0x[0-9a-f]+}} <NEAR>
@@ -72,7 +72,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   jal zero, undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
   jal ra, NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -88,7 +88,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   jal ra, undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
   qc.e.j NEAR
 # CHECK: c.j {{0x[0-9a-f]+}} <NEAR>
@@ -104,7 +104,7 @@ start:
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   qc.e.j undef
 # CHECK: qc.e.j {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
   qc.e.jal NEAR
 # CHECK: c.jal {{0x[0-9a-f]+}} <NEAR>
@@ -120,7 +120,7 @@ start:
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <EXT_JUMP_NEGATIVE>
   qc.e.jal undef
 # CHECK: qc.e.jal {{0x[0-9a-f]+}} <start+{{0x[0-9a-f]+}}>
-# CHECK: R_RISCV_CUSTOM195 undef
+# CHECK: R_RISCV_CHERI_CAPABILITY_CODE undef
 
 
 
diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s
@@ -15,7 +15,7 @@ branch_over_relaxable:
   jal x1, foo
 # CHECK: qc.e.jal 0x0 <branch_over_relaxable>
 # CHECK-NEXT: R_RISCV_VENDOR QUALCOMM
-# CHECK-NEXT: R_RISCV_CUSTOM195 foo
+# CHECK-NEXT: R_RISCV_CHERI_CAPABILITY_CODE foo
 # CHECK-NEXT: R_RISCV_RELAX *ABS*
   bne a0, a1, branch_over_relaxable
 # CHECK-NEXT: bne a0, a1, 0x6 <branch_over_relaxable+0x6>
diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s
@@ -21,13 +21,13 @@ this_section:
 # ASM: qc.e.j undef
 # OBJ: qc.e.j 0x0 <this_section>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE undef{{$}}
 qc.e.j undef
 
 # ASM: qc.e.jal undef
 # OBJ-NEXT: qc.e.jal 0x6 <this_section+0x6>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE undef{{$}}
 qc.e.jal undef
 
 
@@ -42,26 +42,26 @@ qc.e.jal same_section
 # ASM: qc.e.j same_section_extern
 # OBJ-NEXT: qc.e.j 0x18 <this_section+0x18>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE same_section_extern{{$}}
 qc.e.j same_section_extern
 
 # ASM: qc.e.jal same_section_extern
 # OBJ-NEXT: qc.e.jal 0x1e <this_section+0x1e>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE same_section_extern{{$}}
 qc.e.jal same_section_extern
 
 
 # ASM: qc.e.j other_section
 # OBJ-NEXT: qc.e.j 0x24 <this_section+0x24>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE other_section{{$}}
 qc.e.j other_section
 
 # ASM: qc.e.jal other_section
 # OBJ-NEXT: qc.e.jal 0x2a <this_section+0x2a>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE other_section{{$}}
 qc.e.jal other_section
 
 
@@ -81,14 +81,14 @@ same_section_extern:
 # ASM: qc.e.j same_section
 # OBJ: qc.e.j 0x38 <same_section_extern+0x4>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE same_section{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 qc.e.j same_section
 
 # ASM: qc.e.jal same_section
 # OBJ-NEXT: qc.e.jal 0x3e <same_section_extern+0xa>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE same_section{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 qc.e.jal same_section
 
@@ -99,14 +99,14 @@ qc.e.j undef
 # ASM: j undef
 # OBJ: qc.e.j 0x44 <same_section_extern+0x10>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE undef{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 
 qc.e.jal undef
 # ASM: jal undef
 # OBJ: qc.e.jal 0x4a <same_section_extern+0x16>
 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
-# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_CHERI_CAPABILITY_CODE undef{{$}}
 # OBJ-NEXT: R_RISCV_RELAX
 
 .section .text.other, "ax", @progbits
